Datasheet

Philips Semiconductors

PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 14 of 30

9397 750 12999

clock pulse. A slave receiver which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must generate an acknowledge

after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In

this event the transmitter must leave the data line HIGH to enable the master to

generate a stop condition.

9.5 I

C-bus protocol

9.5.1 Addressing

Before any data is transmitted on the I

C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted

after the start procedure.

The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

The PCF8563 slave address is shown in Figure 12.

Fig 11. Acknowledgement on the I

C-bus.

MBC602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig 12. Slave address.

MCE189

1 0 1 0 0 0 1 R/W

group 1

group 2