Datasheet

Philips Semiconductors
PCF8563
Real time clock/calendar
Product data Rev. 04 — 12 March 2004 13 of 30
9397 750 12999
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition
(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as
the STOP condition (P); see Figure 9.
9.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which
are controlled by the master are the slaves (see Figure 10).
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related
Fig 8. Bit transfer.
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9. Definition of start and stop conditions.
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig 10. System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL