Datasheet

Philips Semiconductors

PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 12 of 30

9397 750 12999

3. Clear STOP (control/status 1, bit STOP = 0)

4. Set time registers to desired value

5. Apply 32 clock pulses to CLKOUT

6. Read time registers to see the ﬁrst change

7. Apply 64 clock pulses to CLKOUT

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

8.8 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the

long start-up times experienced by these types of circuits, a mechanism has been

built in to disable the POR and hence speed up on-board test of the device. The

setting of this mode requires that the I

C-bus pins, SDA and SCL, be toggled in a

speciﬁc order as shown in Figure 7. All timings are required minimums.

Once the override mode has been entered, the device immediately stops being reset

and normal operation may commence i.e. entry into the EXT_CLK test mode via

C-bus access. The override mode may be cleared by writing a logic 0 to TESTC.

TESTC must be set to logic 1 before re-entry into the override mode is possible.

Setting TESTC to logic 0 during normal operation has no effect except to prevent

entry into the POR override mode.

9. Characteristics of the I

C-bus

The I

C-bus is for bidirectional, two-line communication between different ICs or

modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up resistor. Data transfer may

be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time will be interpreted as a control signal (see Figure 8).

Fig 7. POR override sequence.

handbook, full pagewidth

MGM664

SCL

500 ns 2000 ns

SDA

8 ms

override active

power up