Datasheet

Philips Semiconductors
PCF85102C-2
256 × 8-bit CMOS EEPROM with I
2
C-bus interface
Product data Rev. 04 — 22 October 2004 4 of 20
9397 750 14216
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Device addressing
[1] The Most Significant Bit (MSB) ‘b7’ is sent first.
A2, A1, A0 are hardware selectable pins.
A system could have up to eight PCF85102C-2 devices on the same I
2
C-bus,
equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.
The eight addresses are defined by the state of the A0, A1, A2 inputs (logic level ‘1’
when connected to V
DD
, logic level ‘0’ when connected to GND). Figure 3 shows the
various address combinations.
Fig 2. Pin configuration.
1
2
3
4
8
7
6
5
A0
A1
A2
V
SS
SDA
SCL
N.C.
V
DD
PCF85102C-2
002aaa248
Table 4: Pin description
Symbol Pin Description
A0 1 address input 0
A1 2 address input 1
A2 3 address input 2
V
SS
4 negative supply voltage
SDA 5 serial data input/output (I
2
C-bus)
SCL 6 serial clock input (I
2
C-bus)
N.C. 7 no connect
V
DD
8 positive supply voltage
Table 5: Device address code
Selection Device code Chip Enable R/W
Bit b7
[1]
b6 b5 b4 b3 b2 b1 b0
Device 1 0 1 0 A2 A1 A0 R/
W