Datasheet

Philips Semiconductors Product specification

82B715I

C bus extender

2001 Mar 06

The capacitance figures for one or more individual I

C bus nodes

should be multiplied by a factor of 10 times, and then added to the

Buffered bus capacitance. Calculation of a new Buffered bus pull-up

resistor will alllow this single pull-up resistor to act for both the

included I

C bus nodes and the Buffered bus. Thus it is possible to

combine some or all of these separate pull-up resistors into a single

resistor on the Buffered bus (the value of which is calculated from

the sum of the scaled capacitances on the Buffered bus). If the

buffer is to be permanently connected into the system then all the

separate pull-up resistors should be combined. But if it is to be

connected by adding it onto an existing system, then only those on

the additional I

C bus system can be combined onto the Buffered

bus if the original system is required to be able to still operate on a

stand-alone basis.

A further restriction is that the maximum pull-up current, with the bus

LOW, should not exceed the I

C bus specification maximum of 3mA,

or 30mA on the Buffered bus. The following formula applies:

30mA u

* 0.4

Where: R

= scaled parallel combination of all pull-up resistors.

If this condition is met, the fall time specifications will also be met.

Figure 4 shows typical loading calculations for the expanded I

bus.

Sx, Sy, I

C Bus, SDA or SCL

Because the two buffer circuits in the 82B715 are identical either

input pin can be used as the I

C Bus SDA data line, or the SCL

clock line.

Lx, Ly, Buffered Bus, LDA or LCL

On the buffered low impedance line side, the corresponding output

becomes LDA and LCL.

, GND — Positive and Negative Supply Pins

In normal use the power supply voltages at each end of the low

impedance line should be comparable. If these differ by a significant

amount, noise margin is sacrificed.