Datasheet

NXP Semiconductors
UM11121
LPCXpresso51U68
UM11121
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© NXP Semiconductors N.V. 2018. All rights reserved.
User manual
Rev 1.1 — 27 April 27, 2018
7 of 22
Circuit ref
Description
Ref section
negative. LPC51U68 current is calculated by dividing the measured voltage at
P2 by the Vsense resistance value of 4.12Ω.
P3
FTDI serial header. In addition to provide a serial output from LPC51U68, the
Target side of the board can be powered from the FTDI header. The
LPC51U68 supports serial ISP boot from the FTDI header.
4.1
P4
External ADC reference input. The pads of this header enable external VREF
(negative and positive) ADC reference voltages to be injected. Pin 1 (indicated
by the square pad) of the connector footprint can connected to the VREFP pin
of the LPC51U68 by removing the zero ohm resistor at SJ from position 1-2
and bridging pads 2-3 instead. Similarly, Pin 3 of P4 can be connected to the
VREFN of the LPC51U68 by removing the zero-ohm resistor at SJ1 from
position 1-2 and bridging pads 2-3 instead.
LPC51U68
User Manual
SW1
LPC51U68 Target WAKE pushbutton. When pressed the WAKE switch will
drive LPC51U68 P0_24 to a low level.
9.3
SW2, SW3
These switches can be used to force the LPC51U68 in to ISP boot modes:
Boot mode
ISP0
ISP1
Vbus (from J5)
I2C/SPI boot
Pressed
Pressed
X
UART boot
Pressed
Not pressed
0
USB Mass storage
Pressed
Not pressed
1
Boot from internal flash
Not pressed
Not pressed
X
After reset these pins may also be used to generate interrupts and/or GPIO
inputs.
9.2
SW4
LPC51U68 Target Reset pushbutton.
9.1
TP1
Ground terminal test point.
n/a
U10
Link2 MCU
n/a
U9
LPC51U68 Target LQFP64 MCU
n/a