Datasheet

NXP Semiconductors
UM11121
LPCXpresso51U68
UM11121
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
User manual
Rev 1.1 — 27 April 27, 2018
6 of 22
Circuit ref
Description
Ref section
J5
Target MCU Power / USB Device connector. Connect this micro USB B-type
connector to a +5V power source when it is desired to power only the Target
MCU, and leave the on-board Link2 debug probe unpowered.
6
J6
Link2 micro USB B-type connector. Powers both the Link2 side of the board
and LPC51U68 Target side of the board. Power the board from this
connector when using the on-board debug probe to debug the LPC51U68
Target MCU.
6
JP1
LPC51U68 Target SWD disable – 2-position jumper pins.
1) Jumper open (default) the LPC51U68 Target SWD interface enabled.
Normal operating mode where the Target SWD is connected to either
the on-board Link2 debug probe or an external debug probe.
2) When the jumper in installed, the LPC51U68 Target SWD interface is
disabled. Use this setting only when the on-board Link2 debug probe
is used to debug an off-board Target MCU.
6
JP2
Buffer power selection. Install jumper in position 1-2 during normal use.
Install in position 2-3 when debugging an off-board target and using the
LPCXpresso51U68 board to power that target via the SWD header (P1).
6
JP3
JP3 is used to isolate the Link2 debug probe (SPI bridge function) from the
LPC51U68 target to prevent leakage current in power critical applications /
current consumption analysis. JP3 needs to be fitted to use the SPI bridging
function between the LPC51U68 and Link2. This jumper is not fitted by default.
n/a
JP4
JP4 (not installed by default) provides a method to disconnect all reset sourced
to the LPC51U68 device except for the reset from the AP control port (J3). If
this jumper is to be used, remove SJ9 first.
n/a
JP5
JP5 can be installed to reduce the voltage sense resistance (used by the on-
board current measurement circuitry) from 8.24 ohms to 4.12 ohms.
5.1
JP6
A current meter may be installed across JP6 terminals to measure the
LPC51U68 current consumption. By default JP6 is shunted by a 0Ω resistor
installed at JS10; remove this shunt to measure current at JP6.
5.1.2
JP7
Link2 (LPC43xx) force DFU boot – 2 position jumper pins.
1) Jumper open (default) for Link2 to follow the normal boot sequence.
The Link2 will boot from internal flash if image is found there. With
the internal flash erased the Link2 normal boot sequence will fall
through to DFU boot.
2) Jumper shunted to force the Link2 to DFU boot mode. Use this
setting to reprogram the Link2 internal flash with a new image or to
use the MCUXpresso IDE to boot the probe.
6.1.3
JP8
Tri-color LED anode voltage enable. By default JP8 is shunted by a 0Ω resistor
installed at JS17. To disable +3.3V to the tri-color led (D2) common anode,
remove the 0Ω at JS17.
5.1
JP9
Power supply voltage selection – 3 position jumper pins.
1) Jumper 1–2: LPC51U68 is powered at 1.8V.
2) Jumper 2–3 (default): LPC51U68 is powered at 3.3V.
n/a
JP10
Target connector USB (J5) VBUS to LPC51U68 connection:
1) Installed (default): JP10 connects VBUS from Target USB connector
to the LPC51U68.
2) Not installed: VBUS from J5 is unconnected.
n/a
P1
10-pin SWD connector – The SWD connector is used to debug the LPC51U68
Target from an external debug probe. The same SWD connector can also be
used to connect the on-board Link2 debug probe to an off-board target MCU
(for this JP1 must be shunted).
6
P2
LPC51U68 VDD current monitor Vsense measurement. The Vsense can be
measured with a volt meter. Pin 1 (square pad) is positive and pin 2 is
5.1.1