Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 63 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
11.2 CoreMark data
Conditions: V
DD
= 3.3 V; active mode; all peripherals except one UART and the SCT disabled in
the SYSAHBCLKCTRL0/1 register; internal pull-up resistors enabled; BOD disabled. Measured
with Keil uVision v.4.73.0.0, C compiler v.5.03.0.76.
Fig 25. CoreMark score
Conditions: V
DD
= 3.3 V; T
amb
= 25 C; active mode; all peripherals except one UART and the SCT
disabled in the SYSAHBCLKCTRL0/1 registers; system clock derived from the IRC; system
oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision
v.4.73.0.0, C compiler v.5.03.0.76.
Fig 26. Active mode: CoreMark power consumption I
DD
aaa-011746
0 12 24 36 48 60 72
2.35
2.4
2.45
2.5
2.55
2.6
2.65
system clock frequency (MHz)
CM score
CM score
CM score
efficiency
cpu
default/low current
aaa-011747
0 12 24 36 48 60 72
0
5
10
15
20
25
30
system clock frequency (MHz)
I
DD
DD
I
DD
(mA)
(mA)
(mA)
default
cpu
efficiency
low-current