Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 60 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
Conditions: V
DD
= 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz - 6 MHz: IRC enabled; PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz to 72 MHz: IRC enabled; PLL enabled.
Fig 19. Active mode: Typical supply current I
DD
versus temperature
Conditions: V
DD
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled;
BOD disabled; low-current mode.
1 MHz - 6 MHz: IRC enabled; PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz to 72 MHz: IRC enabled; PLL enabled.
Fig 20. Sleep mode: Typical supply current I
DD
versus temperature for different system
clock frequencies
aaa-011385
-40 -10 20 50 80 110
0
4
8
12
16
20
temperature (°C)
I
DD
DD
I
DD
(mA)
(mA)
(mA)
12 MHz
24 MHz
48 MHz
60 MHz
72 MHz
36 MHz
6 MHz
1 MHz
aaa-011386
-40 -10 20 50 80 110
0
2
4
6
8
temperature (°C)
I
DD
DD
I
DD
(mA)
(mA)
(mA)
72 MHz
48 MHz
36 MHz
24 MHz
12 MHz
6 MHz
1 MHz
60 MHz