Datasheet

Product data sheet Rev. 1 — 19 February 2014 50 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

In addition, ISP entry the external pins can be disabled without enabling CRP. For details,

see the LPC15xx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using ISP

pin as well. If necessary, the application must provide a flash update mechanism

using IAP calls or using a call to the reinvoke ISP command to enable flash update via

the USART.

In addition to the three CRP levels, sampling of the ISP pins for valid user code can be

disabled. For details, see the LPC15xx user manual.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.