Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 46 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
8.36.1 Internal RC oscillator
The IRC can be used as the clock that drives the system PLL and then the CPU. In
addition, the IRC can be selected as input to various clock dividers and as the clock
source for the USB PLL and the SCT PLL (see Figure 14
). The nominal IRC frequency is
12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC15xx
use the IRC as the clock source. Software can later switch to one of the other available
clock sources.
8.36.2 System oscillator
The system oscillator can be used as a stable and accurate clock source for the CPU, with
or without using the PLL. For USB applications, use the system oscillator to provide the
clock source to USB PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
The system oscillator has a wake-up time of approximately 500 s.
8.36.3 Watchdog oscillator
The low-power watchdog oscillator can be used as a clock source that directly drives the
CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency
is fixed at 503 kHz. The frequency spread over processing and temperature is 40 %.
8.36.4 RTC oscillator
The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a
32 kHz clock output that can be used to obtain the main clock (see Figure 14
).The 32 kHz
oscillator output can be observed on the CLKOUT pin to allow trimming the RTC oscillator
without interference from a probe.
8.37 System PLL, USB PLL, and SCT PLL
The LPC15xx contain a three identical PLLs for generating the system clock, the 48 MHz
USB clock, and an asynchronous clock for the ADCs and SCTs. The system PLL is used
to create the main clock. The SCT and USB PLLs create dedicated clocks for the
asynchronous ADC, the asynchronous SCT clock input, and the USB.
Remark: The USB PLL is available on parts LPC1549/48/47 only.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL
as a clock source. The PLL settling time is 100 s.