Datasheet

Product data sheet Rev. 1 — 19 February 2014 32 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.19.1 Features

• Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions

connected to all digital pins except PIO0_22 and PIO0_23.

• Data transmits of 1 to 16 bits supported directly. Larger frames supported by software.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Up to four Slave Select input/outputs with selectable polarity and flexible usage.

• Supports DMA transfers: SPIn transmit and receive functions work with the system

DMA controller.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.20 I2C-bus interface

The I

C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I

C is a multi-master bus and can be

controlled by more than one bus master connected to it.

The I2C-bus functions are fixed-pin functions and must be enabled through the switch

matrix on the open-drain pins PIO0_22 and PIO0_23.

8.20.1 Features

• Supports standard and fast mode with data rates of up to 400 kbit/s.

• Supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Fail-safe operation: When the power to an I

C-bus device is switched off, the SDA

and SCL pins connected to the I

C-bus are floating and do not disturb the bus.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I

C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I

C bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Supported by on-chip ROM API.