Datasheet

Product data sheet Rev. 1 — 19 February 2014 30 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.16 Input multiplexing (Input mux)

The input mux allows to select from multiple external and internal sources for the SCT

inputs, DMA trigger inputs, and the frequency measure block. The input mux is

implemented as a register interface with one source selection register for each input. The

input mux can for example connect SCT outputs, the ADC interrupts, or the comparator

outputs to the SCT inputs and thus enables the SCT to use a large variety of events to

control the timing operation.

The ADCs and analog comparators also support input multiplexing using source selection

registers as part of their configuration registers.

8.17 USB interface

Remark: The USB interface is available on parts LPC1549/48/47 only.

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports

hot-plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The USB interface consists of a full-speed device controller with on-chip PHY (PHYsical

layer) for device functions.

Remark: Configure the part in default power mode with the power profiles before using

the USB (see Section 8.40.1

). Do not use the USB when the part runs in performance,

efficiency, or low-power mode.

8.17.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, and endpoint buffer memory. The

serial interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

8.17.1.1 Features

• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).

• Supports 10 physical (5 logical) endpoints including one control endpoint.

• Single and double buffering supported.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Supports wake-up from Deep-sleep mode and Power-down mode on USB activity

and remote wake-up.

• Supports SoftConnect functionality through internal pull-up resistor.

• Internal 33  series termination resistors on USB_DP and USB_DM lines eliminate

the need for external series resistors.

• Supports Link Power Management (LPM).