Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 29 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
8.14 GPIO group interrupts (GINT0/1)
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts. For each port/pin connected
to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO
grouped interrupt registers determine which pins are enabled to generate interrupts and
what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block generates an interrupt. If the part is in a power-savings mode, it first
asynchronously wakes the part up prior to asserting the interrupt request. The interrupt
request line can be cleared by writing a one to the interrupt status bit in the control
register.
8.14.1 Features
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The inputs from any number of digital pins can be enabled to contribute to a combined
group interrupt.
• The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
• Enabled interrupts can be logically combined through an OR or AND operation.
• The grouped interrupts can wake up the part from sleep, deep-sleep or power-down
modes.
8.15 DMA controller
The DMA controller can access all memories and the USART, SPI, I2C, and DAC
peripherals using DMA requests. DMA transfers can also be triggered by internal events
like the ADC interrupts, the SCT DMA request signals, or the analog comparator outputs.
8.15.1 Features
• 18 channels with 14 channels connected to peripheral request inputs.
• DMA operations can be triggered by on-chip events. Each DMA channel can select
one trigger input from 24 sources through the input mux.
• Priority is user selectable for each channel.
• Continuous priority arbitration.
• Address cache with four entries.
• Efficient use of data bus.
• Supports single transfers up to 1,024 words.
• Address increment options allow packing and/or unpacking data.