Datasheet

Product data sheet Rev. 1 — 19 February 2014 28 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.12 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function through the switch

matrix are controlled by the GPIO registers. Pins may be dynamically configured as inputs

or outputs. Multiple outputs can be set or cleared in one write operation.

LPC15xx use accelerated GPIO functions.

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

8.12.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

8.13 Pin interrupt/pattern match engine (PINT)

The pin interrupt block configures up to eight pins from the digital pins on ports 1 and 2 for

providing eight external interrupts connected to the NVIC. The input mux block is used to

select the pins.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inputs.

Any digital pin on ports 0 and 1 can be configured through the SYSCON block as input to

the pin interrupt or pattern match engine. The registers that control the pin interrupt or

pattern match engine are located on the IO+ bus for fast single-cycle access.

8.13.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins on ports 0 and 1 as edge- or

level-sensitive interrupt requests. Each request creates a separate interrupt in the

NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

– Pin interrupts can wake up the part from sleep mode, deep-sleep mode, and

power-down mode.

• Pin interrupt pattern match engine

– Up to 8 pins can be selected from all digital pins on ports 0 and 1 to contribute to a

boolean expression. The boolean expression consists of specified levels and/or

transitions on various combinations of these pins.

– Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can be programmed to also generate an RXEV

notification to the ARM CPU.

– The pattern match engine does not facilitate wake-up.