Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 26 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
8.9 Nested Vectored Interrupt controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
8.9.1 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.
• Tightly coupled interrupt controller provides low interrupt latency.
• Controls system exceptions and peripheral interrupts.
• The NVIC supports 47 vectored interrupts.
• Eight programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Support for NMI.
• ARM Cortex-M3 Vector table offset register VTOR implemented.
8.9.2 Interrupt sources
Typically, each peripheral device has one interrupt line connected to the NVIC but can
have several interrupt flags. Individual interrupt flags can also represent more than one
interrupt source.
8.10 IOCON block
The IOCON block configures the electrical properties of the pins such as pull-up and
pull-down resistors, hysteresis, open-drain modes and input filters.
Remark: The pin function and whether the pin operates in digital or analog mode are
entirely under the control of the switch matrix.
Enabling an analog function through the switch matrix disables the digital pad. However,
the internal pull-up and pull-down resistors as well as the pin hysteresis must be disabled
to obtain an accurate reading of the analog input.
8.10.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All pins (except PIO0_22 and PIO0_23) are pulled up to 3.3 V (V
DD
= 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable (on/off) 10 ns glitch filter on 36 pins (PIO0_0 to PIO0_17, PIO0_25 to
PIO0_31, PIO1_0 to PIO1_10). The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
• Digital filter with programmable filter constant on all pins.
8.10.2 Standard I/O pad configuration
Figure 11 shows the possible pin modes for standard I/O pins with analog input function: