Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 24 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
8.7 AHB multilayer matrix
Fig 9. AHB multilayer matrix
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
DMA
AHB-TO-APB
BRIDGE0
AHB-TO-APB
BRIDGE1
EEPROM
HS GPIO
slaves
SRAM2
System
bus
I-code
bus
D-code
bus
masters
FLASH
ROM
AHB MULTILAYER MATRIX
= master-slave connection
DAC
ACMP
WWDT
ADC0
RIT
I2C0 QEI
SWM SPI0
SPI1
USART1PMU
SYSCON
USART2
PINT
GINT0
GINT1
MRT
ADC1
USB
SRAM0
SRAM1
SCTIMER0/PWM
SCTIMER1/PWM
SCTIMER2/PWM
SCTIMER3/PWM
CRC
INPUT MUX RTC
SCTIPU
FLASH CTRL
IOCON EEPROM CTRL
USART2
C_CAN
aaa-010870