Datasheet

LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 February 2014 18 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off
glitch filter. By default, the glitch filter is turned on.
[3] This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant
and provides
standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT,
the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter. By default,
the glitch filter is turned on.
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin
includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake
up the part.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[7] I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode Plus.
[8] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[9] Special analog pin.
[10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
VREFP_ADC 10 13 21 - ADC positive reference voltage. The voltage level on
VREFP_ADC must be equal to or lower than the voltage
applied to V
DDA
. If the ADC is not used, tie VREFP_ADC
to V
DD
.
V
SSA
17 21 31 - Analog ground. V
SSA
should typically be the same voltage
as V
SS
but should be isolated to minimize noise and error.
V
SSA
should be tied to V
SS
if the ADC is not used.
V
SS
41,
20,
40
56,
26,
27,
55
88,
7,
39,
40,
68,
87
- Ground.
Table 3. Pin description with fixed-pin functions
Symbol
LQFP48 LQFP64 LQFP100
Reset
state
[1]
Type Description
Table 4. Movable functions
Function name Type Description
U0_TXD O Transmitter output for USART0.
U0_RXD I Receiver input for USART0.
U0_RTS
O Request To Send output for USART0.
U0_CTS
I Clear To Send input for USART0.
U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode.
U1_TXD O Transmitter output for USART1.
U1_RXD I Receiver input for USART1.
U1_RTS
O Request To Send output for USART1.