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1. General description

The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications

featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a

next generation core that offers system enhancements such as enhanced debug features

and a higher level of support block integration.

The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The LPC15xx includes up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM,

and up to 36 kB of SRAM. The peripheral compliment includes one full-speed USB 2.0

device, two SPI interfaces, three USARTs, one Fast-mode Plus I

C-bus interface, one

C_CAN module, PWM/timer subsystem with four configurable, multi-purpose State

Configurable Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock

module with independent power supply and a dedicated oscillator, two 12-channel/12-bit,

2 Msamples/s ADCs, one 12-bit, 500 kSamples/s DAC, four voltage comparators with

internal voltage reference, and a temperature sensor. A DMA engine can service most

peripherals.

For additional documentation related to the LPC15xx parts, see Section 17 “

References”.

2. Features and benefits

 System:

 ARM Cortex-M3 processor (version r2p1), running at frequencies of up to 72 MHz.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 Serial Wire Debug (SWD) with four breakpoints and two watchpoints.

 Single-cycle multiplier supported.

 Memory Protection Unit (MPU) included.

 Memory:

 Up to 256 kB on-chip flash programming memory with 256 Byte page write and

erase.

 Up to 36 kB SRAM.

 4 kB EEPROM.

LPC15xx

32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and

36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C

Rev. 1 — 19 February 2014 Product data sheet

Summary of content (99 pages)

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LPC15xx 32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and 36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C Rev. 1 — 19 February 2014 Product data sheet 1. General description The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  ROM API support:  Boot loader with boot options from flash or external source via USART, C_CAN, or USB  USB drivers  ADC drivers  SPI drivers  USART drivers  I2C drivers  Power profiles and power mode configuration with low-power mode configuration option  DMA drivers  C_CAN drivers  Flash In-Application Programming (IAP) and In-System Programming (ISP).
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Analog peripherals:  Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC supports two independent conversion sequences. ADC conversion clock can be the system clock or an asynchronous clock derived from one of the three PLLs.  One 12-bit DAC.  Integrated temperature sensor and band gap internal reference voltage.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Single power supply 2.4 V to 3.6 V.  Temperature range 40 °C to +105 °C.  Available as LQFP100, LQFP64, and LQFP48 packages. 3. Applications     Motor control Motion drives Digital power supplies Industrial and medical  Solar inverters  Home appliances  Building and factory automation 4. Ordering information Table 1.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4.1 Ordering options Table 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5. Marking n n Terminal 1 index area 1 aaa-011231 Fig 1. LQFP64/100 package marking Terminal 1 index area Fig 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 25 XTALOUT 26 XTALIN 27 VDD 28 PIO0_17/WAKEUP/TRST 29 SWCLK/ PIO0_19/TCK 30 VBAT 31 RTCXIN 32 RTCXOUT 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS 34 RESET/PIO0_21 35 USB_DP 36 USB_DM 7.
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LPC15xx NXP Semiconductors 25 XTALOUT 26 XTALIN 27 VDD 28 PIO0_17/WAKEUP/TRST 29 SWCLK/ PIO0_19/TCK 30 VBAT 31 RTCXIN 32 RTCXOUT 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS 34 RESET/PIO0_21 35 PIO2_12 36 PIO2_13 32-bit ARM Cortex-M3 microcontroller PIO0_22/I2C0_SCL 37 24 PIO0_16/ADC1_9 PIO0_23/I2C0_SDA 38 23 PIO0_15/ADC1_8 VDD 39 22 PIO0_14/ADC1_7/ SCT1_OUT5 VSS 40 21 PIO0_13/ADC1_6 VSS 41 20 VSS VDD 42 19 PIO0_12/DAC_OUT LPC1517JBD48 PIO0_24/SCT0_OUT6 43 18 PIO0_11/ADC1_3 PIO0_25/ACMP0_I
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LPC15xx NXP Semiconductors 33 PIO1_4 34 PIO1_5 35 XTALOUT 36 XTALIN 37 VDD 38 PIO1_11 39 PIO0_17/WAKEUP 40 SWCLK/ PIO0_19 41 VBAT 42 RTCXIN 43 RTCXOUT 44 SWDIO/ PIO0_20 45 RESET/PIO0_21 46 PIO1_6 47 USB_DP 48 USB_DM 32-bit ARM Cortex-M3 microcontroller PIO0_22 49 32 PIO0_16 PIO0_23 50 31 PIO0_15 PIO1_7 51 30 PIO0_14 VDD 52 29 PIO0_13 PIO1_8 53 28 PIO1_3 PIO1_9 54 27 VSS VSS 55 26 VSS LPC1549JBD64 LPC1548JBD64 LPC1547JBD64 VSS 56 VDD 57 25 PIO1_2 24 PIO0_12 PIO0_9 16 VREF
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LPC15xx NXP Semiconductors 33 PIO1_4 34 PIO1_5 35 XTALOUT 36 XTALIN 37 VDD 38 PIO1_11 39 PIO0_17/WAKEUP 40 SWCLK/ PIO0_19 41 VBAT 42 RTCXIN 43 RTCXOUT 44 SWDIO/ PIO0_20 45 RESET/PIO0_21 46 PIO1_6 47 PIO2_12 48 PIO2_13 32-bit ARM Cortex-M3 microcontroller PIO0_22 49 32 PIO0_16 PIO0_23 50 31 PIO0_15 PIO1_7 51 30 PIO0_14 VDD 52 29 PIO0_13 PIO1_8 53 28 PIO1_3 PIO1_9 54 27 VSS VSS 55 26 VSS LPC1519JBD64 LPC1518JBD64 LPC1517JBD64 VSS 56 VDD 57 24 PIO0_12 PIO0_9 16 VREFN 14 PI
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Most pins are configurable for multiple functions, which can be analog or digital. Digital inputs can be connected to several peripherals at once, however only one digital output or one analog function can be assigned to any on pin. The pin’s connections to internal peripheral blocks are configured by the switch matrix (SWM), the input multiplexer (INPUT MUX), and the SCT Input Pre-processor Unit (SCTIPU).
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO0_8/ADC0_0/TDO LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. 9 12 19 [2] Reset Type state[1] Description I; PU PIO0_8 — General purpose port 0 input/output 8. IO In boundary scan mode: TDO (Test Data Out). PIO0_9/ADC1_1/TDI 12 16 24 [2] I; PU A ADC0_0 — ADC0 input 0. IO PIO0_9 — General purpose port 0 input/output 9. In boundary scan mode: TDI (Test Data In).
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO0_18/ SCT0_OUT5 LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. 13 17 26 [5] Reset Type state[1] Description I; PU PIO0_18 — General purpose port 0 input/output 18. IO On the LQFP64 package, this pin is assigned to U0_TXD in ISP USART mode. On the LQFP48 package, this pin is assigned to CAN0_TD in ISP C_CAN mode.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description with fixed-pin functions IO PIO0_28 — General purpose port 0 input/output 28. A ACMP1_I3 — Analog comparator 1 input 3. IO PIO0_29 — General purpose port 0 input/output 29. A ACMP2_I3 — Analog comparator 2 input 3. O SCT2_OUT4 — SCTimer2/PWM output 4.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description with fixed-pin functions IO PIO1_14 — General purpose port 1 input/output 14. LQFP100 Description LQFP64 Reset Type state[1] LQFP48 Symbol PIO1_14/SCT0_OUT7 - - 12 [5] I; PU O SCT0_OUT7 — SCTimer0/PWM output 7. PIO1_15 - - 15 [5] I; PU IO PIO1_15 — General purpose port 1 input/output 15. 18 [5] I; PU IO PIO1_16 — General purpose port 1 input/output 16.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO2_9 LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. - - 94 [5] Reset Type state[1] Description I; PU PIO2_9 — General purpose port 2 input/output 9. IO On the LQFP100 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. PIO2_10 - - 96 [5] I; PU IO PIO2_10 — General purpose port 2 input/output 10.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64 LQFP100 Pin description with fixed-pin functions LQFP48 Table 3. Symbol Reset Type state[1] Description VREFP_ADC 10 13 21 - ADC positive reference voltage. The voltage level on VREFP_ADC must be equal to or lower than the voltage applied to VDDA. If the ADC is not used, tie VREFP_ADC to VDD. VSSA 17 21 31 - Analog ground.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. LPC15XX Product data sheet Movable functions …continued Function name Type Description U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2. U2_RXD I Receiver input for USART2. U2_SCLK I/O Serial clock input/output for USART1 in synchronous mode. SPI0_SCK I/O Serial clock for SPI0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Movable functions …continued Function name Type Description ACMP1_O O Analog comparator 1 output. ACMP2_O O Analog comparator 2 output. ACMP3_O O Analog comparator 3 output. CLKOUT O Clock output. ROSC O Analog comparator ring oscillator output. ROSC_RESET I Analog comparator ring oscillator reset. USB_FTOGGLE O USB frame toggle.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64 LQFP100 Pins connected to the INPUT MUX and SCT IPU LQFP48 Table 5.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.3 On-chip flash programming memory The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. Flash updates via USB are supported as well. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.5 SRAM The LPC15xx contain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM memory. For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB + 4 kB for 36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB SRAM. The bottom 16 kB, 8 kB, or 4 kB are enabled by the bootloader and cannot be disabled.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.9 Nested Vectored Interrupt controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.9.1 Features • • • • • • • • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3. Tightly coupled interrupt controller provides low interrupt latency.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • • • Digital output driver with configurable open-drain output Digital input: Weak pull-up resistor (PMOS device) enabled/disabled Digital input: Weak pull-down resistor (NMOS device) enabled/disabled Digital input: Repeater mode enabled/disabled Digital input: Input digital filter configurable on all pins Digital input: Input glitch filter enabled/disabled on select pins Analog input VDD VDD open-drain enable strong pull-up ou
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.12 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function through the switch matrix are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC15xx use accelerated GPIO functions. • An entire port value can be written in one instruction.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.14 GPIO group interrupts (GINT0/1) The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts. For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.16 Input multiplexing (Input mux) The input mux allows to select from multiple external and internal sources for the SCT inputs, DMA trigger inputs, and the frequency measure block. The input mux is implemented as a register interface with one source selection register for each input.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.18 USART0/1/2 Remark: All USART functions are movable functions and are assigned to pins through the switch matrix. Do not connect USART functions to the open-drain pins PIO0_22 and PIO0_23. Interrupts generated by the USART peripherals can wake up the part from Deep-sleep and power-down modes if the USART is in synchronous mode, the 32 kHz mode is enabled, or the CTS interrupt is enabled. 8.18.1 Features • Maximum bit rates of 4.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.19.1 Features • Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions connected to all digital pins except PIO0_22 and PIO0_23. • Data transmits of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.21 C_CAN Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller can build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a high level of reliability.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller digital signal from/to pins analog peripheral analog signal from/to pins digital peripheral digital signal internal analog signal internal ANALOG IN TRIGGER SWITCH MATRIX THRESHOLD CROSSING INTERRUPTS ADC0/ADC1 4 VDDA DIVIDER TEMP SENSOR VOLTAGE REFERENCE SCT0 MATCH/ MATCHRELOAD OUTPUTS 8 x PWM OUT TIMER0 SCT1 MATCH/ MATCHRELOAD OUTPUTS 8 x PWM OUT TIMER1 TIMER2 SCT2 MATCH/ MATCHRELOAD OUTPUTS TIMER3 SCT3 MATCH/ MATCHRELOA
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller analog peripheral analog signal from/to pins digital peripheral INPUT MUX DMA digital signal from/to pins digital signal internal analog signal internal 4 VOLTAGE REFERENCE SCT IPU INPUT MUX TEMP SENSOR TIMER1 (SCT1) TIMER2 (SCT2) NVIC OUTPUTS TIMER0 (SCT0) VDDA DIVIDER THRESHOLD CROSSING INTERRUPTS TRIGGER SWITCH MATRIX ANALOG IN ADC0/ADC1 SWITCH MATRIX ACMP0 ACMP1 ACMP2 ACMP3 OUTPUTS ANALOG IN TIMER3 (SCT3) DAC_SH
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller – 8 inputs and 10 outputs – DMA support • Counter/timer features: – Configurable as two 16-bit counters or one 32-bit counter. – Counters clocked by system clock or selected input. – Configurable as up counters or up-down counters. – Configurable number of match and capture registers. Up to 16 match and capture registers total.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • 10 outputs (some outputs are connected to multiple locations) – Three outputs connected to external pins through the switch matrix as movable functions. – Five outputs connected to external pins through the switch matrix as fixed-pin functions. – Two outputs connected to the SCTIPU to sample or latch input events.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller – The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state. – Selected events can limit, halt, start, or stop a counter. – Events control state changes, outputs, interrupts, and DMA requests. – Match register 0 can be used as an automatic limit.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Four registers to indicate which specific input sources caused the abort input to the SCTs. • Four additional outputs which can be sampled at certain times and latched at others before being routed to SCT inputs. • Nine abort inputs. Any combination of the abort inputs can trigger the dedicated abort input of each SCT. 8.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.24.1 Features • • • • 12-bit successive approximation analog-to-digital converter. • • • • Two configurable conversion sequences with independent triggers. 12-bit conversion rate of 2 MHz. Input multiplexing among 12 pins and up to 4 internal sources. Internal sources are the temperature sensor voltage, internal reference voltage, core voltage regulator output, and VDDA/2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.26.1 Features • Seven selectable inputs. Fully configurable on either the positive side or the negative input channel. • 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either positive or negative comparator input. • Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog voltage supply. • 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • When the ADC is accurately calibrated, the internal voltage reference can be used to measure the power supply voltage. This requires calibration by recording the ADC code of the internal voltage reference at different power supply levels yielding a different ADC code value for each supply voltage level.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.31 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.31.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.35 Power domains The LPC15xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD) is used to operate the RTC whenever VDD is present.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.36.1 Internal RC oscillator The IRC can be used as the clock that drives the system PLL and then the CPU. In addition, the IRC can be selected as input to various clock dividers and as the clock source for the USB PLL and the SCT PLL (see Figure 14). The nominal IRC frequency is 12 MHz. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC15xx use the IRC as the clock source.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.38 Clock output The LPC15xx feature a clock output function that routes the internal oscillator outputs, the PLL outputs, or the main clock an output pin where they can be observed directly. 8.39 Wake-up process The LPC15xx begin operation by using the 12 MHz IRC oscillator as the clock source at power-up and when awakened from Deep power-down mode. This mechanism allows chip operation to resume quickly.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.40.3 Deep-sleep mode In Deep-sleep mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down and the flash is in stand-by mode.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.41 System control 8.41.1 Reset Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller In addition, ISP entry the external pins can be disabled without enabling CRP. For details, see the LPC15xx user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.42 Emulation and debugging Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M3 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC15xx is in reset.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit Ilatch I/O latch-up current (0.5VDD(IO)) < VI < (1.5VDD(IO)); - 100 mA Tstg storage temperature 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Symbol Thermal resistance value (C/W): ±15 % Parameter Conditions Typ Unit thermal resistance junction-to-ambient JEDEC (4.5 in  4 in) 0 m/s 64 C/W 1 m/s 55 C/W 2.5 m/s 50 C/W 0 m/s 96 C/W 1 m/s 76 C/W LQFP48 ja 8-layer (4.5 in  3 in) 67 C/W jc thermal resistance junction-to-case 13 C/W jb thermal resistance junction-to-board 16 C/W 0 m/s 51 C/W 1 m/s 45 C/W 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 11. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) VDDA analog supply voltage Vref reference voltage VBAT battery supply voltage IDD supply current Min Typ[1] Max Unit 2.4 3.3 VDDA V 2.4 3.3 3.6 V on pin VREFP_DAC_VDDCMP 2.4 - VDDA V on pin VREFP_ADC 2.7 - VDDA V 2.4 3.3 3.6 V - 4.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol IBAT Parameter battery supply current Conditions Min Deep power-down mode; VDD = VDDA = 3.3 V; VBAT = 3.0 V [13] VDD and VDDA tied to ground; VBAT = 3.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol VI Parameter Conditions input voltage VDD  2.4 V [16] Min Typ[1] Max Unit 0 - 5.0 V [18] VO output voltage VIH HIGH-level input voltage VIL LOW-level input voltage Vhys hysteresis voltage VOH HIGH-level output voltage VDD = 0 V 0 - 3.6 V output active 0 - VDD V 0.7VDD - - V - - 0.3VDD V 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions Min Typ[1] Max Unit 1.8 - - V VIL LOW-level input voltage - - 1.0 V Vhys hysteresis voltage 0.32 - - V Zout output impedance 28 - 44 Ω VOH HIGH-level output voltage 2.9 - - V VOL LOW-level output voltage - - 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [13] RTC running or not running. [14] Characterized on samples. Not tested in production. [15] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [16] Including voltage on outputs in tri-state mode. [17] VDD supply voltage must be present. [18] Tri-state outputs go into tri-state mode in Deep power-down mode.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.1 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. aaa-011384 20 IDD (mA) 72 MHz 16 60 MHz 12 48 MHz 36 MHz 8 24 MHz 4 12 MHz 6 MHz 1 MHz 0 2.4 2.6 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011385 20 IDD (mA) 72 MHz 16 60 MHz 12 48 MHz 36 MHz 8 24 MHz 4 12 MHz 6 MHz 1 MHz 0 -40 -10 20 50 80 temperature (°C) 110 Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011234 400 IDD (μA) 380 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 360 340 320 300 280 -40 -10 20 50 80 temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled. Use API power_mode_configure() with mode parameter set to DEEP_SLEEP and peripheral parameter set to 0xFF. Fig 21.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011236 4 IDD (μA) 3 2 3.6 V 3.3 V 1 2.4 V 0 -40 -10 20 50 80 temperature (°C) 110 VBAT = 0 V. Fig 23. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-011333 4 IBAT (μA) 3 2 1 0 -40 -10 20 50 80 temperature (°C) 110 VBAT = 3.3 V; VDD floating. Fig 24.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 CoreMark data aaa-011746 2.65 CM score 2.6 2.55 cpu 2.5 2.45 efficiency 2.4 default/low current 2.35 0 12 24 36 48 60 system clock frequency (MHz) 72 Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL0/1 register; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.73.0.0, C compiler v.5.03.0.76. Fig 25.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at Tamb = 25 C.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 12. Power consumption for individual analog and digital blocks …continued Peripheral Typical supply current in mA Notes n/a 12 MHz 72 MHz USART0 - 0.02 0.15 - USART1 - 0.02 0.16 - USART2 - 0.02 0.15 - C_CAN - 0.50 3.00 USB - 0.10 0.50 Comparator ACMP0/1/2/3 - 0.01 0.03 - ADC0 - 0.05 0.33 - ADC1 - 0.04 0.33 - temperature sensor - 0.03 0.03 internal voltage reference/band gap 0.03 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011258 50 IOL OH (mA) 40 -40 °C 25 °C 90 °C 105 °C 30 20 10 0 0 0.1 0.2 0.3 0.4 VOL (V) 0.5 Conditions: VDD = 3.3 V; on pins PIO0_22 and PIO0_23. Fig 28. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL aaa-011263 10 VOL (V) 8 -40 °C 25 °C 90 °C 105 °C 6 4 2 0 0 0.1 0.2 0.3 0.4 IOL (mA) 0.5 Conditions: VDD = 3.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011276 3.3 IOH (mA) -40 °C 25 °C 90 °C 105 °C 3.1 2.9 2.7 0 3 6 9 VOH (V) 12 Conditions: VDD = 3.3 V; standard port pins. Fig 30. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH aaa-011277 0 Ipu pd (μA) -20 105 °C 90 °C 25 °C -40 °C -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 31.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011278 80 Ipu (μA) 60 -40 °C 25 °C 90 °C 105 °C 40 20 0 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 32. Typical pull-down current Ipd versus input voltage VI LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 February 2014 © NXP B.V. 2014. All rights reserved.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash/EEPROM memory Table 13. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. W&+&/ W&+&; W&/&+ W&/&; 7F\ FON DDD Fig 33. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 12.3 Internal oscillators Table 16. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1].
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 17. Symbol fosc(int) Dynamic characteristics: Watchdog oscillator Parameter Conditions internal oscillator frequency - [2] Min Typ[1] Max Unit - 503 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. 12.4 I/O pins Table 18.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 19. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; values guaranteed by design.[2] Symbol Parameter tSU;DAT [1] data set-up time [9][10] Conditions Min Max Unit Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_22 and PIO0_23 50 - ns See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.6 SPI interfaces The maximum data bit rate is 17 Mbit/s in master mode and in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_22 and PIO0_23. Table 20. SPI dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 1 ns.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7F\ FON 6&. &32/ 6&. &32/ W'6 026, '$7$ 9$/,' W'+ '$7$ 9$/,' WY 4 0,62 WK 4 '$7$ 9$/,' W'6 026, '$7$ 9$/,' W'+ '$7$ 9$/,' WY 4 0,62 '$7$ 9$/,' &3+$ '$7$ 9$/,' WK 4 &3+$ '$7$ 9$/,' DDD Fig 37. SPI slave timing LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 February 2014 © NXP B.V. 2014. All rights reserved.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.7 USART interface The maximum USART bit rate is 15 Mbit/s in synchronous mode master mode and 18 Mbit/s in synchronous slave mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_22 and PIO0_23. Table 21. USART dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 10 ns.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.8 SCT output timing Table 22. SCT output dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V Cl = 10 pF. Simulated skew (over process, voltage, and temperature) of any two SCT fixed-pin output signals; sampled at the 50 % level of the falling or rising edge; values guaranteed by design.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 24. 12-bit ADC static characteristics Tamb = 40 C to +105 C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. Symbol Parameter Conditions [1] VIA analog input voltage Cia analog input capacitance fclk(ADC) ADC clock frequency VDDA 2.7 V fs sampling frequency VDDA 2.7 V Min Max 0 VDDA V - 0.32 pF 50 MHz VDDA 2.4 V VDDA 2.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 25. DAC static and dynamic characteristics VDDA = 2.4 V to 3.6 V; Tamb = 40 C to +105 C unless otherwise specified; CL = 100 pF; RL = 10 k.. Symbol Parameter Conditions Min Typ Max Unit 500 kSamples/s [1] fc(DAC) DAC conversion frequency - -  RO output resistance - 300 ts settling time - - 2.5 s ED differential linearity error - - +/-0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 26. Internal voltage reference static and dynamic characteristics Symbol Parameter Conditions VO output voltage Tamb = 40 C to +105 C ts(pu) power-up settling time to 99% of VO [1] Min Typ Max Unit 875 - 925 mV 125 s Tamb = 25 C 905 - - mV [1] Maximum and minimum values are measured on samples from the corners of the process matrix lot.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 27. Temperature sensor static and dynamic characteristics VDDA = 2.4 V to 3.6 V Symbol Parameter Conditions DTsen sensor temperature accuracy Tamb = 40 C to +105 C EL linearity error Tamb = 40 C to +105 C power-up settling time ts(pu) [1] [2][3] to 99% of temperature sensor output value Min Typ Max Unit - - 5 C - - 5 C - 81 110 s [1] Absolute temperature accuracy.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 29. Comparator characteristics VDDA = 3.0 V. DLY = 0x0 in the analog comparator CTRL register for shortest propagation delay setting. See the LPC15xx user manual UM10736. Symbol Parameter Conditions Min Typ Max Unit VP > VM - 48 - A VM > VP - 38 - A Static characteristics supply current IDD VIC common-mode input voltage 0 - VDDA V DVO output voltage variation 0 - VDD V Voffset offset voltage VIC = 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 30. Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value - - 30 s ts(sw) switching settling time to 99% of voltage ladder output value - - 20 s Table 31. Comparator voltage ladder reference static characteristics VDD(3V3) = 3.3 V; Tamb = -40 C to + 105C; external or internal reference.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14. Application information 14.1 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 44) or bus-powered device (see Figure 45). On the LPC15xx, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx VDD REGULATOR USB_CONNECT USB R1 1.5 kΩ VBUS RS = 33 Ω USB_DP RS = 33 Ω USB_DM USB-B connector VSS aaa-010821 Fig 45. USB interface on a bus-powered device Remark: When a bus-powered circuit as shown in Figure 45 is used or, for a self-powered device, when the VBUS pin is not connected, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block. This ties the VBUS signal HIGH internally. 14.1.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 46. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 46), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 32.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.4 RTC oscillator component selection The 32 kHz crystal must be connected to the part via the RTCXIN and RTCXOUT pins as shown in Figure 48. If the RTC is not used, the RTCXIN pin can be grounded. LPC1xxx L RTCXIN RTCXOUT = CL CP XTAL RS CX1 CX2 aaa-010822 Fig 48. RTC oscillator components Select Cx1 and Cx2 based on the external 32 kHz crystal used in the application circuitry.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 52.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 53.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 54.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. References [1] LPC15xx User manual UM10736: http://www.nxp.com/documents/user_manual/UM10736.pdf [2] LPC15xx Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC15XX.pdf 18. Revision history Table 34. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC15XX v.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.41.1 8.41.2 8.41.3 8.42 9 10 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 13 14 14.1 14.1.1 14.2 14.3 14.4 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brownout detection . . . . . . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) Emulation and debugging . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . .