Datasheet
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Note:
ESR Control
Resistor
Layout Note:
Route antenna as shown
in reference design
POWER SUPPLY
Note: Max 100mA
Note:
ESR Control
Resistor
0805 0805
Layout Note:
L1-L4 as close as
possible to IC
Layout Note:
Place J15 and JI5 in a dual footprint
Place J17 and JI7 in a dual footprint
(there is an "1" and an "i")
VDD
3V3_ARD
VDD
VDD VDD
VDD
+5V_ARD
+5V_PC
+5V_ARD
+5V_DB15
+5V_PC
3V3_ARD
VDD
VDD
+5V_DB15
Drawing Title:
Size Document Number Rev
Date: Sheet
of
Page Title:
Designer:
Drawn by:
Approved :
6501 W illiam Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH37525 - SPF37525 C
OM-SE050ARD
C
Monday, March 18, 2019
Schematic
Catalin Neacsu
Rodolfo V
Catalin Neacsu
3 3
____X____
Drawing Title:
Size Document Number Rev
Date: Sheet
of
Page Title:
Designer:
Drawn by:
Approved :
6501 W illiam Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH37525 - SPF37525 C
OM-SE050ARD
C
Monday, March 18, 2019
Schematic
Catalin Neacsu
Rodolfo V
Catalin Neacsu
3 3
____X____
Drawing Title:
Size Document Number Rev
Date: Sheet
of
Page Title:
Designer:
Drawn by:
Approved :
6501 W illiam Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
ICAP Classification: CP: IUO: PUBI:
SCH37525 - SPF37525 C
OM-SE050ARD
C
Monday, March 18, 2019
Schematic
Catalin Neacsu
Rodolfo V
Catalin Neacsu
3 3
____X____
J17
HDR 2X3
DNP
1 2
3 4
65
C4
2pF
DNP
J13
HDR TH 1X3
JUMPER(DEFAULT) = 2-3
1
2
3
J19
HDR TH 1X3
JUMPER(DEFAULT) = 2-3
1
2
3
J29 JUMPER
R7
820
J28 JUMPER
J22
CON 1X4
DNP
MKS1854-6-0-404
1
2
3
4
U2
MIC5233-3.3YS
GND
2
OUT
3
IN
1
TAB
4
R1
3.3K
J26
HDR 1X2 TH
SILK = GND
JUMPER(DEFAULT) = 1-2
1
2
L4
330OHM
1 2
R10
820
J37
HDR 1X2 TH
JUMPER(DEFAULT) = OPEN
1
2
J30 JUMPER
R5
0
R2
3.3K
J36
HDR 1X2 TH
OPEN
1
2
R9
820
C3
68pF
DNP
J31 JUMPER
C7
0.033UF
R6
0
J38
HDR 1X2 TH
JUMPER(DEFAULT) = OPEN
1
2
J12
HDR TH 1X3
JUMPER(DEFAULT) = 2-3
1
2
3
R3
3.3K
J15
HDR 2X3
DNP
1 2
3 4
65
J11
HDR 1X10
SILK = ISO7816
1
2
3
4
5
6
7
8
9
10
J32 JUMPER
JI5
HDR 2X2
JUMPER(DEFAULT) = 3-4
1
2
3
4
J24
HDR 2X3
JUMPER(DEFAULT) = 1-2
1 2
3 4
65
J7
HDR TH 1X3
JUMPER(DEFAULT) = 2-3
1
2
3
J2
SSW -110-03-G-S
1
2
3
4
5
6
7
8
9
10
J3
DB15
DNP
5
9
4
8
3
7
2
6
1
M2
M1
10
11
12
13
14
15
JI7
HDR 2X2
JUMPER(DEFAULT) = 3-4
1
2
3
4
J35
HDR 1X2 TH
OPEN
1
2
J33 JUMPER
R8
820
L1
330OHM
1 2
J1
SSW -108-03-G-S
1
2
3
4
5
6
7
8
J18
HDR TH 1X3
JUMPER(DEFAULT) = 1-2
1
2
3
J6
HDR TH 1X3
JUMPER(DEFAULT) = 1-2
1
2
3
J16
HDR TH 1X3
JUMPER(DEFAULT) = 2-3
1
2
3
C5
0.033UF
J34 JUMPER
L2
330OHM
1 2
U1
SE050C
ISO_14443_LB
1
NC_2
2
ISO_7816_IO
3
NC_4
4
NC_5
5
NC_6
6
NC_7
7
NC_8
8
I2C_SDA
9
I2C_SCL
10
EPAD
21
NC_20
20
VSS
19
VCC
18
ISO_14443_LA
17
ISO_7816_IO2
16
VOUT
15
ISO_7816_RST
14
ISO_7816_CLK
13
VIN
12
ENA
11
J10
HDR 1X2 TH
JUMPER(DEFAULT) = OPEN
1
2
C1
2.2UF
J4
SSW -106-03-G-S
1
2
3
4
5
6
R4
3.3K
J27
HDR TH 1X3
DNP
1
2
3
C6
0.01UF
J14
HDR 2X3
JUMPER(DEFAULT) = 3-4
1 2
3 4
65
J9
HDR 1X2 TH
JUMPER(DEFAULT) = OPEN
1
2
J25
HDR 1X2 TH
SILK = GND
JUMPER(DEFAULT) = 1-2
1
2
L3
330OHM
1 2
C2
2.2UF
J8
SSW -108-03-G-S
1
2
3
4
5
6
7
8
ISO7816
VIN
ARD_SDA
SE_ENA
ARD_SCL
ARD_SCL_R3
SE_CLK
ARD_SCK
SE_VIN
SE_RST
ARD_RST
+3V3_LIN
ARD_RST
SE_LB
SE_LA
SE_IO2
SE_IO1
SE_SDA
SE_SCL
SE_ENA
SE_CLK
SE_RST
ANT_LB
ANT_LA
SE_SCL
SE_IO2
SE_CLK
SE_SDA
SE_SCL
SE_LA
DB_LA
DB_LB
SE_VIN
SE_RST
SE_VOUT
DB_LA
DB_LB
SE_ENA
ARD_ENA
SE_ENA
ARD_MOSI
ARD_SDA_R3
SE_SDA
SE_SCL
SE_IO1
SE_VOUT
SE_VDD
SE_VOUT
ISO7816
SE_LB
SE_VOUT
SE_IO1
ARD_D0
ARD_ENA
SE_VDD
SE_VIN
SE_VOUT
SE_SDA
SE_IO1
SE_IO2
6 Schematics
AN12395 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved.
Application note Rev. 0.4 — 4 June 2019
534310