Datasheet
Table 69. Revision history (continued)
Revision Date Description of changes
• JTAG interface timing
• Debug trace timing specifications
• Electrostatic discharge (ESD) specifications - Removed the VESD(CDM) specs for corner
pins.
7 08/2018 • GPIO speed at various voltage levels - Added the text "The maximum rise time for all GPIO
pins is 1 ms" to the existing note.
• Power sequencing requirements - Updated the last bullet to "The maximum rise time for the
POR and RESET.........this pin can increase the problem.".
8 12/2018 • Changed all instances of XOSC to FXOSC throughout the document.
• In Table 1 - For S32V232 changed "Up to 800 MHz Dual ARM Cortex-A53 (single cluster)" to
"Up to 1000 MHz Dual ARM Cortex-A53 (single cluster)" and in communications row removed
all the text and added text "Same as S32V234" for S32V232.
• In Ordering information - Changed text from "The orderable part numbers of this chip are in
the table below" to "An example of orderable part numbers of this chip are in the table below".
• In GPIO speed at various voltage levels - Added the Drive Strength "001" and "010" in the
"GPIO rise/fall times (1.8 V range)", "GPIO rise/fall times (2.5 V range)" and "GPIO rise/fall
times (3.3 V range)" tables.
• In Features - Removed the text "ARM TrustZone (TZ) architecture support" and added text
"Secure vs non-secure applications separation supported via ARM v8 exception level support
in the ARM Cortex A53 clusters and its extension via XRDC on SoC level".
• In Table 6 updated the following:
• Replaced descriptive text with orderable part number.
• Removed @ 125 C from each row.
• Split the row "DD_LV_CORE" into "DD_LV_CORE (static)" and "DD_LV_CORE
(dynamic)" into separate rows.
• Added "T
j
" as the temperature in the footnote.
• Added further static power entries. Added values for 125 T
j
and 105 T
j
for
VDD_LV_CORE (Static).
• Added parameters "VDD_HV_ADV" and "VDD_REFH_ADC".
• In DDR3 and DDR3L timing parameters added Note "DDR3 and DDR3L timing parameters
are compliant with JESD79-3F and JESD79-3-1A.01 specifications respectively".
• In LPDDR2 timing parameter added Note "LPDDR2 timing parameters are compliant with
JESD209-2B specification".
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 89