Datasheet

Table 69. Revision history (continued)
Revision Date Description of changes
• In PCB routing guidelines, added a note under the "CLK/Addess/Commands" section. And
updated the third point under the section for clarification.
• In Table 4, row 2 and 3 has been split into sub-sections for different I/O voltages.
• In Table 6, updated max value for VDD_HV_LFASTPLL when "PLL operating with 320 MHz
(LFAST used)". Value is changed from 24 mA to 26 mA.
• In Table 17, updated T
ADC
at T
J
= 40 °C to 125 °C, from +/- 5 °C to +/- 6 °C.
• In Table 6, updated descriptions for VDD_HV_CSI and VDD_LV_CSI. The string "not
powered?" is changed to "IP Powered and Disabled".
• In Main oscillator electrical characteristics, updated the section to remove references of 24
MHz FXOSC support.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), updated the topic title and
added a paragraph describing voltage restriction with eMMC booting.
• In Table 6, removed the footnotes from the "Max Values" column, and added one to the
VDD_LV_CORE entry.
• In Table 20, updated the frequency values for "PLL input clock".
• In Table 21, updated the "Input Frequency" values.
• Updated the specs in following tables:
• Table 30
• Table 32
• Table 33
• Table 35
• Removed the table "PLL maximum frequencies" from the section PLL electrical specifications.
• In DFS electrical specifications, updated mfn division factor from [0:255] to [1:255], and
updated the footnote from the Table 21.
5
03/2018 • This device is qualified now, so removed the footnote from Table 23 that said "Device
qualification is not complete.".
• Corrected "Operating Max Supply Voltage" for "3.3 V DGO Voltage Domain" in Table 3 to 3.6
V.
• Corrected Block diagram to add DRAM-ECC to MMDC_1 block, similar to it was with
MMDC_0.
• Updated the specs for VDD_LV_CORE in Table 6.
• Updated max values for T
DRB
and T
ERLB
in Table 66.
6 08/2018 • GPIO speed at various voltage levels - Added a note at the end of the section.
• Power sequencing requirements - Added one new point to the bullet list mentioning the
maximum rise time for POR signal.
• Boot Configuration Pins Specification - Added two notes in this section.
• Table 57 - Updated "Maximum serial data rate" spec from "80 to 1.5 Gbps" to "80 to 1500
Mbps".
• Following changes are made throughout the document for better clarification:
• DSE[2:0] changed to SIUL2_MSCRn[DSE].
• ipp_dse<1:0> changed to SIUL2_MSCRn[DSE].
• FSEL[1:0] changed to SIUL2_MSCRn[SRE].
• ipp_fsel changed to SIUL2_MSCRn[SRE].
• Deleted the test condition about ipp_do.
• Added a note to the following sections to clarify that to match with the measurements given in
the section you must ensure the configuration mentioned. That may not be the default
configuration of the chip after reset.
• QuadSPI AC specifications
• DSPI timing
• Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
• Ethernet Switching Specifications
• MII/RMII Serial Management channel timing (MDC/MDIO)
• Interface to TFT panels
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
88 NXP Semiconductors