Datasheet

Table 69. Revision history (continued)
Revision Date Description of changes
• In Thermal Monitoring Unit (TMU), changed all occurrences of “Temperature Sensor” to
“Thermal Monitoring Unit”.
• In 48 MHz FIRC electrical characteristics, min and max value of “IRCOSC frequency variation
with respect to supply and temperature after process trimming” has been changed from -5 to
-10 and +5 to +10 %.
• In QuadSPI AC specifications deleted sentence "DDR configurations are applicable when
used without learning enabled."
• Added a note in DSPI timing.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) changed the introductory
paragraph.
• Renamed topic "SD/eMMC4.3 (Single Data Rate) AC Timing" to "SDR Mode Timing
Specifications". In this topic SDR mode timing specifications deleted the introductory
paragraph and deleted the existing figure. Two new figures Figure 23 and Figure 24 are
added. Modified Table 37.
• Renamed topic "SD/eMMC4.4/5.0 (Dual Data Rate) eSDHCv3 AC Timing" to "DDR Mode
Timing Specifications". In this topic DDR mode timing specifications, deleted the introductory
paragraph and replaced the existing figure with four new figures (Figure 25, Figure 26, Figure
27, Figure 28).
• In DSPI timing changed the note from "DSPI on this chip neither supports interaction with a
Slave in MTFE mode nor acts as one" to "DSPI Timing specs on this chip are valid with Slave
in Classic Mode only."
• In Ethernet Switching Specifications, ” statement "For RGMI, output load is 15 pF and pad
settings are DSE[2:0] = 111 and FSEL[1:0] = 11" is changed to "For RGMII, output load is 5
pF and pad settings are DSE[2:0] = 111 and FSEL[1:0] = 11."
• Added topic MII/RMII Serial Management channel timing (MDC/MDIO).
• In Video input unit (VIU) timing specifications heading "Video input unit (VIU) electrical
specifications" changed to "Video input unit (VIU) timing specifications".
• Added topic Boot performance matrix.
• In Power sequencing requirements :
• added note "VDD_HV_ADV must be powered for using LFAST interface". Changed
“VREFH_ADC should never be more than 100 mV above VDD_HV_ADV” to
“VREFH_ADC should never differ from VDD_HV_ADV by more than 100 mV at any
time including during power-up or power-down”.
• Changed the sentence from "DDR0_VREF0 and DDR1_VREF0 supplies are expected
to be 0.5 of VDD_HV_DDR0 and VDD_HV_DDR1 I/O supplies and are to track
VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver” to
"DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_DDR0_IO
and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1
supply variations as measured at the receiver”.
• Updated the statement "VDD_HV_CSI and VDD_LV_CSI should be powered up
together on board to prevent any electrical crossover currents" to "VDD_HV_CSI and
VDD_LV_CSI supplies should be powered up within 50 ms of each other".
3.1
07/2017 • The only changes between S32V234 Rev 3.1 and Rev 3 is the removal of "Confidential
Proprietary" from the footer.
4 11/2017 • In Ordering information, added a table mentioning the production part numbers with
respective feature configurations.
• In Table 20, updated SSCG modulation depth values.
• In Features, updated the statement for "APEX2-CL Image cognition processor" to remove the
mention of OpenCL 1.2 support.
• In Features, updated the first statement under "Memory interfaces" with the correct LPDDR2/
DDR3/DDR3L operating specs.
• Updated LPDDR2 and DDR3 operating clock rate and data rate in Figure 1.
• In Feature Set, updated the "Memory Interfaces" entry for the correct operating data rate and
clock rate of LPDD2 and DDR3.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 87