Datasheet

Table 69. Revision history
Revision Date Description of changes
• Updated the footnote in minimum and maximum values of “Common mode voltage”
(Receiver).
• Changed minimum value of “Differential input voltage” (Receiver) from 100 to 150 mV.
• In Table 44 changed minimum and maximum value of RX_CLK duty cycle.
• In Table 45 :
• changed minimum and maximum value of TX_CLK duty cycle and minimum value of
Out delay from TX_CLK.
• included "TX_CLK to Output Valid" and "TX_CLK to Output Invalid".
• In Table 46 removed the foot note from "Characteristic".
• In Table 50 :
• Changed minimum value of “Data hold time0” and “Data setup time” from 0 to 25 ns,
and 0 to 250 (standard mode); 100 (fast mode) respectively
• Added note "ipg_clk frequency should be greater than 5 MHz for standard mode and 20
MHz for fast mode" to minimum value of “Data setup time”
• Updated the column "Number"
• In Table 51, minimum value of “Stop condition setup time” has been changed from 10 to 11
IPS bus cycle.
• In Table 52, changed Display pixel clock period from 6.4 to 6.66 ns.
• In Table 53, changed pixel clock period from 6.36 to 6.66 ns.
• In Table 54, changed description "VIU data setup time" to "VIU Data/Hsync/Vsync setup time"
and "VIU data hold time" to "VIU Data/Hsync/Vsync hold time".
• In Table 55, removed "Contention Line Receiver DC Specifications".
• In Table 58, Data to Clock Setup Time and Clock to Data Hold Time are updated to include
condition where the PHY is used to a maximum data rate of 1.0Gbps and data rates greater
than 1.0Gbps.
• In Table 61, updated Clock frequency.
• In Table 66 :
• changed minimum and maximum values of “Destructive Reset Sequence, BIST
disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of “Functional Reset Sequence Long,
Unsecure Boot, BIST disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of ”Functional Reset Sequence Short,
Unsecure Boot, BIST disabled” from 5 ms to 2 µs and 6 ms to 7 µs.
• Added Table 68 and a paragraph preceding it “Each supply group mentioned in the table
below can be independently powered up/down from the other supply groups. Supply domains
belonging to the same supply group are supposed to be ganged together on board level (with
appropriate noise isolation) to allow this group to power up/down together”.
• All IRC and IRCOSC in the document changed to FIRC.
• In Features, modified JPEG and H.264 information.
• Removed hysteresis information from Features, Table 1, and from Table 11.
• Modified content in Family comparison.
• Added topic Operation above maximum operating conditions.
• Updated Ordering information
• In Power consumption, modified the statement “These specifications are design targets and
are subject to change per device characterization” to “These specifications are subject to
change per device characterization.”
• In PCB routing guidelines changed the subheading from "DDR3 PCB design" to "DDR3/
DDR3L PCB design".
• Added topic GPIO speed at various voltage levels.
• In DDR pads, deleted table "DDR operating conditions".
• In ADC electrical specifications, Updated the note to “While measuring scaled supply voltages
on ADC Channels, Maximum (+5/-10%) variation can be expected .”
• In Main oscillator electrical characteristics, added crystal information.
• In ADC electrical specifications added the note “While measuring scaled supply voltages on
ADC Channels, Maximum 10% variation can be expected”.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
86 NXP Semiconductors