Datasheet

Table 69. Revision history
Revision Date Description of changes
• In Table 22 :
• unit for Total Jitter has been changed from ps to ns.
• removed max Deterministic and max Random jitter specifications; added footnote in
max Total Jitter.
• In Table 23 :
• Made modification in DDR mode.
• Updated values of QuadSPI_SOCCR[FDCC_FB] and QuadSPI_SOCCR[FDCC_FA] for
SDR and DDR mode (internal DQS Mode) and added footnote “Device qualification is
not complete.”
• Deleted Table "QuadSPI input timing (DDR mode) specifications with learning"
• In Table 25 changed Minimum value of Chip select output setup time and Chip select output
hold time.
• In Table 26
• changed maximum value of SCK Clock Frequency and updated configuration. Also,
changed table caption
• changed the minimum value of "Setup time for incoming data".
• In Table 27 :
• deleted "Chip select output setup time" and "Chip select output hold time".
• changed the maximum value of "Output Data Valid" and minimum value of "Output Data
Hold".
• In Table 28, updated minimum value of parameters “Setup time for incoming data” and “Hold
time for incoming data”.
• In Table 29, updated maximum value of “Ck to Ck2 skew max” and minimum value of “Ck to
Ck2 skew min”.
• In Table 30 changed symbol and minimum value of DDR4, DDR5, DDR6, and DDR7.
• In Table 31 modified minimum value of DDR26 from 540 to 563 ps.
• In Table 32 changed the symbol and minimum value of DDR17 and DDR18.
• In Table 33 changed the symbol and minimum value of parameters CKE setup time, CKE hold
time, CA setup time, and CA hold time.
• In Table 34 changed the minimum value of LP26.
• In Table 35 changed the symbol and minimum value of LP17 and LP18.
• In Table 36 :
• Updated footnotes to include changes in PCSSCK, CSSCK, PASC, ASC values.
• Updated footnotes in minimum timing of parameter DSPI cycle time, PCS to SCK delay,
and After SCK delay.
• In Table 37 changed the heading of table from "SD/eMMC4.3 interface timing specification" to
"SDR mode timing specification".
• In Table 38 changed the heading of table from "SD3.0/eMMC4.5 interface timing
specification" to "DDR mode timing specification" and updated parameter "Clock Frequency
(eMMC4.5 DDR)" to "Clock Frequency (eMMC4.4 DDR)".
• In Table 39 :
• updated min, typ, and max values of V
OS_DRF
and |Δ
VOD_DRF
|
• deleted R
OUT_DRF
and V
HYS_DRF
• modified R
IN_DRF
• added LFAST Clock characteristics
• parameter Rise/Fall time (10% - 90% of swing) is changed to Rise/Fall time (20% - 80%
of swing) and minimum and maximum values of the parameter have been changed from
0.26 to 0.1 ns and 1.5 to 0.73 ns.
• added footnote “Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF
Cload and 100 Ohm termination resistor load”.
• Updated minimum and maximum value of “Common mode voltage” (Transmitter) from
1.125 to 1.1 V and 1.375 to 1.475 V.
• Updated maximum value of “Common mode voltage” (Receiver) from 1.6 to 1.5 V.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 85