Datasheet

Table 69. Revision history
Revision Date Description of changes
use cases are removed, and PCIE_VPH (5 GHz operation) use case has been changed
from 30 to 32 mA. Max values of both PCIE_VP and PCIE_VPH (for both cases) have
been included.
• modified the table heading. Removed Front Camera (w power binning) from
VDD_LV_CORE and updated max values for “Adder 4x A53 CPU with Dhrystone MIPS
running on each CPU @1 GHz” from 1.0 A to 1.4 A.
• removed "Simulation values" column.
• PCIE_VPH limits changed for “5 GHz operation (PCIe 2.0)” from 40 mA to 50 mA and
“Reset/Idle” from 11 mA to 20 mA.
• minimum and maximum values of PMC Band Gap Reference value have been changed
from 1185 to 1176 mV, and 1215 to 1224 mV respectively.
• In Table 11 :
• added the note ”After bootup, application software should switch to manual voltage
detect mode using VSEL_x settings of SRC_GPR14 register to ensure optimum
performance of the GPIO pads. Please refer to SRC chapter in the Reference Manual
for the register details.”
• changed the maximum value of Input current (no pull-up/down) from 1 to 8 μA.
• removed “Input Hysteresis”
• maximum value of parameter “Input current (50 kilohm PU)” has been changed from
100 to 150 μA.
• maximum value of parameter “Input current (100 kilohm PU)” has been changed from
50 to 60 μA.
• removed parameter “pad keeeper resistance” and "maximum external resistor value
that is guaranteed to overdrive the pad keeper".
• maximum value of parameter “Input current (50 kilohm PD)” with test condition Vin=0
has been changed from 1 to 8 μA. Also, when Vin = Vdd, maximum value of Input
current (33 kilohm PU), Input current (50 kilohm PU), and Input current (100 kilohm PU)
have been changed from 1 to 6 μA.
• test conditions "Ioh=-1 mA" changed to "Ioh=-100 μA" and "Ioh= 1 mA" changed to
"Ioh=-100 μA".
• In Table 13, Table 14, and Table 15,
• Added Vih (DC) and Vil (DC) specifications .
• All tri-state supply current items are removed and updated test conditions of "High-level
output voltage" and "Low-level output voltage".
• Maximum value of parameter “ Input current (no pullup/pulldown)” has been changed
from 3 to 5 μA, 3 to 5 μA, and 2.5 to 5 μA, respectively.
• In Table 13, removed parameter “Rod_keep”. Updated minimum, typical, and maximum value
of parameter Rkeep.
• In Table 14, removed parameter “Rod_keep”.
• In Table 15, removed parameter “Rod_keep” and deleted footnote “Note that the Jedec
LPDDR2 specification (JESD209-2B) supersedes any specification in this document”.
• In Table 16
• updated ADC Input Clock frequency
• added ADC Conversion clock frequency
• removed conditions of Sample time and Conversion time
• removed all information about parameter “Max positive/negative injection” and modified
“Total unadjusted error” in “TUE”.
• In Table 18, modified the minimum and maximum values of V
IH
and V
IL
.
• In Table 20 :
• Changed maximum value of SSCG modulation depth from -6% to -5.4%, and added
condition STEPSIZE x STEPNO < 18432.
• Removed “PLL VCO frequency” and “PLL output clock PHI0”, and deleted footnote "All
PLLs have same specifications. PLL programming should take maximum clock
frequencies as per Reference Manual recommendation”.
• Added Table 20.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
84 NXP Semiconductors