Datasheet

Table 69. Revision history (continued)
Revision Date Description of changes
In Table 59, updated minimum value of TCK Cycle Time and the footnote. Also, added CJTAG TCK
Cycle Time and updated maximum value of TCK Rise and Fall Times.
Added DDR3L mode and DDR3L mode DC electrical specifications.
Removed LPDDR2 I/O AC specifications.
Deleted the word "Dual" from "Dual QuadSPI supporting Execute-In-Place (XIP)" in "Features"
section as there is only one QuadSPI.
Changed all instances of XOSC to FXOSC throughout the document.
Changed all instances of MIPI-CSI2, MIPI, and CSI2 to MIPICSI2 throughout the document.
2.1 06/2015 Overall:
• Editorial changes.
3 04/2017 • Editorial changes.
• Updated Figure 1.
• Modified Figure 4.
• Modified Figure 6.
• Modified Figure 7.
• Updated Figure 29.
• Updated Figure 38.
• Updated Figure 43.
• Updated Figure 48.
• Removed Figure "DSPI modified transfer format timing – slave, CPHA = 0" and Figure "DSPI
modified transfer format timing — slave, CPHA = 1".
• In Table 1, updated ARM Cortex-A53 Core feature for S32V232 from “Up to 600 MHz Quad
ARM Cortex-A53” to “Up to 800 MHz Dual ARM Cortex-A53 (single cluster)”.
• In Table 4 :
• added the footnote "All the grounds viz. VSS, VSS_XOSC,VSS_PMC and
VSS_HV_ADV are tied together at the package level” in Common ground voltage.
• minimum operating voltage of V
DD_HV_IO_ETH
has been changed from 1.71 V to 1.5 V,
and maximum value of DDR I/O supply voltage LPDDR2 changed from 1.26 V to 1.30
V.
• parameter “Supply ramp rate” has been changed to “Supply ramp rate for all supplies
on the device”
• added LFAST IO bank supply (V
DDIO_LFAST
) in the list of symbols for "1.8 V supply
voltage (for analog circuits, PLLs)"
• In Table 5 :
• added Band Gap Reference value of PMC.
• maximum value of trimmed VTH threshold of VDD_LV_CORE_SOC (low voltage
monitoring) has been changed from 939 to 946 mV, and maximum values of trimmed
VTL and VTH threshold of VDD_LV_CORE_SOC (high voltage monitoring) have been
changed from 1081 to 1093, and 1096 to 1093 mV, respectively.
• In Table 6 :
• modified table footnotes to clarify that power numbers are estimated for 1.01 V and 125
°C.
• VDD_HV_LFASTPLL Simulation values (Maximum) and Maximum Values of Use cases
"PLL operating with 320 MHz (LFAST used)” and "PLL not operational (LFAST not
used)” have been modified.
• use case “eFuse reading happening” of VDD_HV_EFUSE and its specifications are
removed.
• max simulation values of MIPICSI2 interface operating as per MIPICSI not used (not
powered?) in VDD_HV_CSI and VDD_LV_CSI have been changed from .1 mA to 1.6
mA and 11 mA to 15 mA.
• for PCIE_VP and PCIE_VPH, Powered down (leakage only) use case has been
changed to Reset/idle. Max simulation values for PCIE_VP and PCIE_VPH (Reset/idle)
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 83