Datasheet

Table 69. Revision history (continued)
Revision Date Description of changes
2 06/2015 Overall:
• Editorial changes.
Added topic PCB routing guideliness.
Added topic RESET pin glitch filter specifications.
In Table 16, added the sentence "For internal ADC channels, the minimum sampling time required
is 3 microsecond" in the foot note on "Sample time".
In Power Management Controller (PMC) electrical specifications, changed the introductory
paragraph. Added Low Voltage Detector for IRC (VDD_HV_OSC).
In Table 4, modified minimum value of 3.3 V input/output supply voltage.
In Reset sequence description, updated both "External reset sequence long, BIST enabled" and
"Destructive reset sequence, BIST enabled" images.
In Table 18, updated the condition of Oscillator start-up time from f
OSC
= 24,40 MHz to f
FXOSCHS
=
24,40 MHz.
In Power sequencing requirements, changed VREFL_ADC to VREFH_ADC, VDD_HV_CSI1/2 to
VDD_HV_CSI, and VDD_LV_CSI1/2 to VDD_LV_CSI.
In Table 11, added footnote in ovdd.
In Table 6, changed VS4 to S32V234 and VS2 to S32V232.
Made extensive changes in QuadSPI AC specifications.
In Table 4, added Supply ramp rate specifications.
In Table 6, changed maximum value of vdd_hv_pll from 30 mA to 35 mA and maximum value of
vdd_lv_pll from 55 mA to 80 mA.
In DDR3 and DDR3L timing parameters , added a note.
In Table 30, updated the table title to include DDR3L. Also updated minimum value of DDR4. DDR5,
DDR6, and DDR7 and changed units of DDR1 and DDR2.
In Table 31, updated the table title to include DDR3L. Also updated minimum value of DDR26.
In Table 32, updated the table title to include DDR3L. Updated minimum values of DDR17 and
DDR18, and units of DDR21 and DDR22.
In Table 33, updated LP1 and LP2 symbols and units.
In Figure 15, changed figure title from “LPDDR3 write cycle” to “LPDDR2 write cycle”.
In Table 35, updated minimum value of LP18, and minimum and maximum value of LP21. Also
updated units of LP21, LP22, and LP23.
Updated topic titles DDR SDRAM Specific Parameters (DDR3, DDR3L, and LPDDR2), DDR3 and
DDR3L timing parameters , DDR3 and DDR3L read cycle, and DDR3 and DDR3L write cycle.
Updated figure titles Figure 10, Figure 11, and Figure 12.
In Reset sequence description, added value of external pull up resistor as 10-15 kiloohm.
In Table 19, modified the parameter "IRCOSC frequency variation afterprocess trimming" to
"IRCOSC frequency variation with respect to supply and temperature after process trimming".
Updated Table 17.
In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), added the sentence
"uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper functioning
of uSDHC external interface".
In Table 60, updated maximum value of TCK Rise and Fall Times.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
82 NXP Semiconductors