Datasheet

• DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of V
DD_DDR0_IO
and V
DD_DDR1_IO
supplies and are to track V
DD_HV_DDR0
and
VDD_HV_DDR1
supply
variations as measured at the receiver. Peak-to-Peak noise on DDR0_VREF0 and
DDR1_VREF0 supplies should be between +/- 15 mV.
• The maximum rise time for the POR and RESET signal is 1 ms. Very slow ramps
can induce bounces in the input read state during the transition from logic low to
logic high, which causes the part getting locked in a self-reset loop. Any external
noise on this pin can increase the problem.
NOTE
VDD_HV_ADV must be powered for using LFAST interface.
Each supply group mentioned in the table below can be independently powered up/down
from the other supply groups. Supply domains belonging to the same supply group are
supposed to be ganged together on board level (with appropriate noise isolation) to allow
this group to power up/down together. Following supply groups have been tested for
power sequencing tests:
Table 68. Supply groups tested for power sequencing
Supply Group No. Voltage domain S32V234 power supplies
1 3.3 V V
DD_GPIO0
2 1.8 V/3.3 V V
DD_GPIO1
3 1.8 V/3.3 V V
DD_GPIO2
4 1.8 V/3.3 V V
DD_HV_IO_VIU0
5 1.8 V/3.3 V V
DD_HV_IO_VIU1
6 1.8 V/3.3 V V
DD_HV_DIS
7 1.8 V/3.3 V V
DD_HV_IO_FLA
8 1.5 V/1.8 V/2.5 V/3.3 V V
DD_HV_IO_ETH
9 1.8 V V
DD_HV_PLL
, V
DD_HV_LFASTPLL
, V
DD_HV_FXOSC
,
V
DD_HV_PMC
, V
DD_HV_EFUSE
, V
DD_HV_DDR
,
P
CIE_VPH
, V
DD_HV_CSI
, V
DDIO_LFAST
10 1.0 V V
DD_LV_CORE_SOC
, V
DD_LV_CORE_ARM
, V
DD_LV_GPU
,
V
DD_LV_PLL
, P
CIE_VP
, V
DD_LV_CSI
11 1.8 V V
DD_HV_ADV
, V
REFH_ADC
12 1.2 V/1.35 V/1.5 V V
DD_DDR_IO
12 Revision history
Table 69. Revision history
Revision Date Description of changes
1 03/2015 Initial release.
Table continues on the next page...
Revision history
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 81