Datasheet

PHASE1,2 PHASE3 DRUN
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
Application
Fuse
Init
Device
Config
Ex ecut ion
T
FRL, min
< T
RESET
< T
FRL, max
Boot
code
execution
Figure 62. Functional reset sequence long
PHASE3 DRUN
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
Application
Execution
T
FRS, min
< T
RESET
< T
FRS, max
Boot
code
execution
Figure 63. Functional reset sequence short
The reset sequences shown in Figure 62 and Figure 63 are triggered by functional reset
events. RESET (Active-low) is driven low during these two reset sequences only if the
corresponding functional reset source (which triggered the reset sequence) was enabled to
drive RESET (Active-low) low for the duration of the internal reset sequence. See the
RGM_FBRE register in the device reference manual for more information.
11
Power sequencing requirements
While designing the system, it is important to take care of following constraints:
• P
CIE_VP
and
PCIE_VPH
supplies should be powered up within 50 ms of each other.
• V
DD_HV_CSI
and
VDD_LV_CSI
supplies should be powered up within 50 ms of each
other.
• V
REFH_ADC
should never differ from V
DD_HV_ADV
by more than 100 mV at any time
including during power-up or power-down.
Power sequencing requirements
S32V234 Data Sheet, Rev. 8, 01/2019
80 NXP Semiconductors