Datasheet

driving it low. The reset sequence durations given in Table 66
are applicable only if the internal reset sequence is not
prolonged by an external reset generator keeping RESET
(Active-low) asserted low beyond the last Phase3.
PHASE0 PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUNBIST
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
Establish Fuse
Device
Application
FIRC and
PWR
Init
Config
Fuse
Init
Device
Config
T
DRB, min
< T
RESET
< T
DRB, max
Boot
Code
Execution
LBIST
Execution
MBIST
Self-test
Setup
Boot Code
Execution
Figure 59. Destructive reset sequence, BIST enabled
PHASE0 PHASE1,2 PHASE3 DRUN
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
Establish
Device
Application
FIRC and
PWR
Init
Config
Execution
T
DR, min
< T
RESET
< T
DR, max
Fuse
Boot
Code
Execution
Figure 60. Destructive reset sequence, BIST disabled
PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUNBIST
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
Fuse
Application
Fuse
Init
Device
Config
T
ERLB, min
< T
RESET
< T
ERLB, max
Boot
Code
execution
Boot
code
execution
Execution
LBIST
MBIST
Init
Self-test
Setup
Device
config
Figure 61. External reset sequence long, BIST enabled
Reset sequence
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 79