Datasheet

1.7
4.1
7.4
0 5 10
CSE AUTHENTICATION TIME
FROM DDR
Time in ms
Authentication Length
256 kB 128 kB 32 kB
0.2
0.82
1.6
25.3
DDR(FAST BOOT)
Time in ms
Boot Length
4 MB 256 kB 128 kB 32kB
3.47 ms
CLOCK
INITIALIZATION
AND
QSPI INIT
RESET
AFTER SELF
TEST
JUMP TO
APPLICATION
CODE
CSE FIRMWARE DOWNLOAD +
APPLICATION IMAGE AUTHENTICATION
(SECURE BOOT)
APPLICATION IMAGE DOWNLOAD
DCD EXECUTION
TO CONFIGURE
DDR
Figure 58. Boot diagram
10.3
Reset sequence description
The figures in this section show the internal states of the device during the five different
reset sequences. The doted lines in the figures indicate the starting point and the end point
for which the duration is specified in Table 66.
The application code execution starts when boot code has finished all the mandatory
tasks and jumps over the downloaded image. The download time and authentication time
will vary as per Application code image size.
"EXT_POR" pin (Active Low) is recommended to be de-asserted after external supplies
became stable. Deassertion of EXT_POR pin triggers the start of reset sequence.
The following figures show the internal states of the device during the execution of the
reset sequence and the possible states of the RESET (Active-low) signal pin.
NOTE
RESET (Active-low) is a bidirectional pin. The voltage level on
this pin can either be driven low by an external reset generator
or by the device internal reset circuitry. A high level on this pin
can only be generated by an external pullup resistor (10-15
kiloohm) which is strong enough to overdrive the weak internal
pulldown resistor. The rising edge on RESET (Active-low) in
the following figures indicates the time when the device stops
Reset sequence
S32V234 Data Sheet, Rev. 8, 01/2019
78 NXP Semiconductors