Datasheet

Table 66. RESET sequences
1
(continued)
No. Symbol Parameter T
Reset
Unit
Min Typ Max
4 T
FRL
Functional Reset Sequence Long, Unsecure Boot, BIST disabled 50 — 90 µs
5 T
FRS
Functional Reset Sequence Short, Unsecure Boot, BIST disabled 2 — 7 µs
1. All the Reset durations assume boot code execution time for Execute-in-place for QuadSPI booting, Unsecure mode with
Trimmed FIRC module. Boot code is using execution using PLL and no DCD download is assumed. Secure Boot duration
and DCD download time is dependent on the given application image. DCD downloads and application image download/
authentication times will be over and above these durations.
10.2 Boot performance matrix
Total Boot execution time will be the addition of DCD execution time to configure DDR
and application image download time.
Table 67. Boot execution time
Boot
sourc
e
QSPI_
CLOC
K
CSE_
CLOC
K
CM4
clock
(core
count
er
regist
er
clock)
QSPI
config
uratio
n
SRAM
(FAST
BOOT)
Non
secur
e
DCD
execut
ion
time
for
DDR
DDR(F
AST
BOOT)
DDR(F
AST
BOOT)
DDR(F
AST
BOOT)
DDR(F
AST
BOOT)
Authe
nticati
on
time
from
DDR
Authe
nticati
on
time
from
DDR
Authe
nticati
on
time
from
DDR
Boot
Length
in bytes
100
MHz
133
MHz
133
MHz
HyperFl
ash
4Mbyte
s
NA 4 MB 256 KB 128 KB 32 KB NA NA NA
Authent
ication
Length
in bytes
100
MHz
133
MHz
133
MHz
HyperFl
ash
NA NA NA NA NA NA 256 KB 128 KB 32 KB
Time in
ms
100
MHz
133
MHz
133
MHz
HyperFl
ash
27.302 3.47 25.347 1.63 0.819 0.211 7.4165
25
4.15405
5
1.7064
075
Reset sequence
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 77