Datasheet

Table 64. External interrupt timing (continued)
No. Symbol Parameter Conditions Min Max Unit
2 t
IPWH
IRQ pulse width high - 3 - t
CYC
3 t
ICYC
IRQ edge to edge time
1
- 6 - t
CYC
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
1
2
3
Figure 57. External interrupt timing
Thermal attributes
7.1
Thermal attributes
Table 65. Thermal Resistance Data
Symbol Parameter Conditions Estimate
s (w/
Lid)
Unit
R
θJA
Junction to Ambient Natural Convection
1
Single layer board (1s) 29 °C/W
R
θJA
Junction to Ambient Natural Convection
1
Four layer board (2s2p) 18 °C/W
R
θJMA
Junction to Ambient (@200 ft/min)
1
Single layer board (1s) 20 °C/W
R
θJMA
Junction to Ambient (@200 ft/min)
1
Four layer board (2s2p) 13 °C/W
R
θJB
Junction to Board
2
Four layer board (2s2p) 6 °C/W
R
θJCtop
Junction to Case (Top)
2
Four layer board (2s2p) 1 °C/W
Junction to Lid Top
3
Four layer board (2s2p) 0.32 °C/W
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
3. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the
cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the
thermal resistance of the interface layer between the package and cold plate.
7
Thermal attributes
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 75