Datasheet

TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
Figure 55. JTAG boundary scan timing
6.7.2
Debug trace timing specifications
Measurements are with a load of 20 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 61. Debug trace operating behaviors
Symbol Description Min. Max. Typical Unit
T
cyc
Clock frequency — 150 — MHz
T
wl
Low pulse width 2.8 — 2.95 ns
Table continues on the next page...
Debug specifications
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 73