Datasheet

Table 60. PCIe JTAG AC electrical characteristics
1
(continued)
# Symbol Characteristic Min Max Unit
10 t
JCMPS
JCOMP Setup Time to TCK Low 40 - ns
11 t
BSDV
TCK Falling Edge to Output Valid - 600
5
ns
12 t
BSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
- 600 ns
13 t
BSDHZ
TCK Falling Edge to Output High Impedance - 600 ns
14 t
BSDST
Boundary Scan Input Valid to TCK Rising Edge 15 - ns
15 t
BSDHT
TCK Rising Edge to Boundary Scan Input Invalid 15 - ns
1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing.
4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
5. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
TCK
1
2
2
3
3
Figure 52. JTAG test clock input timing
Debug specifications
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 71