Datasheet
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 59. JTAG pin AC electrical characteristics
1
# Symbol Characteristic Min Max Unit
1 t
JCYC
JTAG/SWD TCK Cycle Time
2
25
3
- ns
CJTAG TCK Cycle Time 50
4
- ns
2 t
JDC
TCK Clock Pulse Width 40 60 %
3 t
TCKRISE
TCK Rise and Fall Times (40% - 70%) - 1 ns
4 t
TMSS
, t
TDIS
TMS, TDI Data Setup Time 5 - ns
5 t
TMSH
, t
TDIH
TMS, TDI Data Hold Time 5 - ns
6 t
TDOV
TCK Low to TDO Data Valid - 18
5
ns
7 t
TDOI
TCK Low to TDO Data Invalid 0 - ns
8 t
TDOHZ
TCK Low to TDO High Impedance - 18 ns
9 t
JCMPPW
JCOMP Assertion Time 100 - ns
10 t
JCMPS
JCOMP Setup Time to TCK Low 40 - ns
11 t
BSDV
TCK Falling Edge to Output Valid - 600
6
ns
12 t
BSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
- 600 ns
13 t
BSDHZ
TCK Falling Edge to Output High Impedance - 600 ns
14 t
BSDST
Boundary Scan Input Valid to TCK Rising Edge 15 - ns
15 t
BSDHT
TCK Rising Edge to Boundary Scan Input Invalid 15 - ns
1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing
4. Cycle time is 50 ns assuming full cycle timing. Cycle time is 100 ns assuming half cycle timing
5. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
6. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
Table 60. PCIe JTAG AC electrical characteristics
1
# Symbol Characteristic Min Max Unit
1 t
JCYC
TCK Cycle Time
2
25
3
- ns
2 t
JDC
TCK Clock Pulse Width 40 60 %
3 t
TCKRISE
TCK Rise and Fall Times (40% - 70%) - 1 ns
4 t
TMSS
, t
TDIS
TMS, TDI Data Setup Time 5 - ns
5 t
TMSH
, t
TDIH
TMS, TDI Data Hold Time 5 - ns
6 t
TDOV
TCK Low to TDO Data Valid - 21
4
ns
7 t
TDOI
TCK Low to TDO Data Invalid 0 - ns
8 t
TDOHZ
TCK Low to TDO High Impedance - 21 ns
9 t
JCMPPW
JCOMP Assertion Time 100 - ns
Table continues on the next page...
Debug specifications
S32V234 Data Sheet, Rev. 8, 01/2019
70 NXP Semiconductors