Datasheet

6.6.3.5 Data to Clock timing
Figure 51. Data to Clock timing definition
Table 58. Data to Clock timing specifications
Symbol Parameters Test conditions Min Typ Max Unit
TCLK
P
Clock Period — 1.33 — 25 ns
UI
INST
UI Instantaneuous — .667 — 12.5 ns
T
SETUP
Data to Clock Setup Time — 0.2
1
— — UI
INST
0.15
2
— — UI
INST
T
HOLD
Clock to Data Hold Time — 0.2
1
— — UI
INST
0.15
2
— — UI
INST
1. when D-PHY is supporting maximum data rate > 1 Gbps.
2. when D-PHY is supporting maximum data rate = 1 Gbps.
6.6.3.6 NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR
owned or controlled by any of the authors or developers of this material or MIPI®. The
material contained herein is provided on an “AS IS” basis and to the maximum extent
permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS,
and the authors and developers of this material and MIPI hereby disclaim all other
warranties and conditions, either express, implied or statutory, including, but not limited
to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike
effort, of lack of viruses, and of lack of negligence.
Display modules
S32V234 Data Sheet, Rev. 8, 01/2019
68 NXP Semiconductors