Datasheet

Table 53. LCD Interface Timing Parameters—Access Level (continued)
Symbol Description Min Max Unit
t
DV
TFT interface VSYNC valid after pixel clock _ 3 ns
t
DV
TFT interface DE valid after pixel clock _ 3 ns
t
HO
TFT interface output hold time for data and control bits 0 _ ns
Relative skew between the data bits _ 1.5 ns
Figure 47. LCD Interface Timing Parameters—Access Level
6.6.2
Video input unit (VIU) timing specifications
f
PIX_CLK
t
DHD
t
DSU
Clock
Data/Hsync/Vsync
Figure 48. VIU timing diagram
Table 54. VIU timing parameters
Parameter Description Min Typ Max Unit
f
PIX_CK
VIU pixel clock
frequency
— — 100 MHz
t
DSU
VIU Data/Hsync/
Vsync setup time
3 — — ns
t
DHD
VIU Data/Hsync/
Vsync hold time
1 — — ns
Display modules
S32V234 Data Sheet, Rev. 8, 01/2019
64 NXP Semiconductors