Datasheet

Table 52. LCD interface timing parameters—horizontal and vertical (continued)
Symbol Characteristic Unit
t
SH
Screen height DELTA_Y * t
HSP
ns
t
VSP
VSYNC (frame) period (PW_V + BP_V + FP_V + DELTA_Y ) * t
HSP
ns
LD[23:0]
DELTA_X
1
2
3 Invalid Data
Invalid Data
PCLK
t
PCP
t
PWH
t
HSP
t
BPH
t
SW
t
FPH
HSYNC
DE
Start
of line
Figure 45. Horizontal sync timing
LD[23:0]
(Line Data)
DELTA_Y
1
2
3 Invalid Data
Invalid Data
t
HCP
t
PWV
t
VSP
t
BPV
t
SH
t
FPV
HSYNC
HSYNC
DE
Start of
Frame
Figure 46. Vertical sync pulse
6.6.1.3
Interface to TFT LCD panels—access level
This section provides the access level timing parameters of the LCD interface.
Table 53. LCD Interface Timing Parameters—Access Level
Symbol Description Min Max Unit
t
CKP
Pixel Clock Period 6.66 _ ns
t
DV
TFT interface data valid after pixel clock _ 3 ns
t
DV
TFT interface HSYNC valid after pixel clock _ 3 ns
Table continues on the next page...
Display modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 63