Datasheet

VSYNC
HSYNC
DE
LD[23:0]
PCLK
m-1 m1 2 3
HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n
LINE
n-1
Figure 44. TFT LCD interface timing overview
6.6.1.2 Interface to TFT LCD Panels—Pixel Level Timings
This section provides the horizontal timing (timing of one line), including both the
horizontal sync pulse and data. All parameters shown in the figure below are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high. Pixel clock inversion and a
flexible programmable pixel clock delay are also supported. They are programmed via
the clock divide . The DELTA_X and DELTA_Y parameters are programmed via the
DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the
HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 52. LCD interface timing parameters—horizontal and vertical
Symbol Characteristic Unit
t
PCP
Display pixel clock period 6.66 ns
t
PWH
HSYNC pulse width PW_H * t
PCP
ns
t
BPH
HSYNC back porch width BP_H * t
PCP
ns
t
FPH
HSYNC front porch width FP_H * t
PCP
ns
t
SW
Screen width DELTA_X * t
PCP
ns
t
HSP
HSYNC (line) period (PW_H + BP_H + FP_H + DELTA_X ) * t
PCP
ns
t
PWV
VSYNC pulse width PWV * t
HSP
ns
t
BPV
VSYNC back porch width BP_V * t
HSP
ns
t
FPV
VSYNC front porch width FP_V * t
HSP
ns
Table continues on the next page...
Display modules
S32V234 Data Sheet, Rev. 8, 01/2019
62 NXP Semiconductors