Datasheet

Display modules
6.6.1 Display Control Unit (2D-ACE) Parameters
6.6.1.1 Interface to TFT panels
This section provides the LCD interface timing for a generic active matrix color TFT
panel.
Measurements are with a load of 20 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
In the figure below
1
, signals are shown with positive polarity. The sequence of events for
active matrix interface timing:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 150 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
6.6
1. LD[23:0]” signal is “line data,” an aggregation of the 2D-ACE’s RGB signals—R[0:7], G[0:7] and B[0:7].
Display modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 61