Datasheet

2. pg_clk frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode.
Table 51. IIC SCL and SDA output timing specifications
Number Symbol Parameter Value Unit
Min Max
1
1
— D Start condition
hold time
6 — IP bus cycle
2
2
1
— D Clock low time 10 — IP bus cycle
1
3
3
— D SCL/SDA rise
time
— 99.6 ns
4
1
— D Data hold time 7 — IP bus cycle
1
5
1
— D SCL/SDA fall
time
— 99.5 ns
6
1
— D Clock high time 10 — IP bus cycle
1
7
1
— D Data setup time 2 — IP bus cycle
1
8
1
— D Start condition
setup time (for
repeated start
condition only)
20 — IP bus cycle
1
9
1
— D Stop condition
setup time
11 — IP bus cycle
1
1. Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed.
The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
2. Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
3. Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA
takes to reach a high level depends on external signal capacitance and pullup resistor values.
Figure 43. IIC input/output timing
6.5.8
LINFlex timing
The maximum bit rate is 1.875 MBit/s.
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
60 NXP Semiconductors