Datasheet

Table 1. Feature Set (continued)
Feature S32V234 S32V232
• ECC/parity error support for its
memories
• Generic timers
ARM Cortex-M4 Core • Up to 133 MHz
• 16 KB/16 KB I-/D- L1 Cache
• 32+32 KB tightly coupled memory
(TCM)
• ECC/parity support for its memories
• Same as S32V234
Clocks • Phase Locked Loops (PLLs)
• 1 external crystal ocillators (FXOSC)
• 1 FIRC
• Same as S32V234
System, protection and power
management features
• Flexible run modes to consume lower
power based on application needs.
• Peripheral clock enable registers can
disable clocks to unused modules,
thereby reducing currents
• Low and high voltage warning and
detect
• Hardware CRC module to support fast
cyclic redundancy checks (CRC)
• 120-bit unique chip identifier
• Hardware watchdog
• Safe eDMA controller with 32 channels
(with DMAMUX)
• Extended Resource Domain Controller
• Same as S32V234
Safety concept • ISO 26262, ASIL level target as per
safety concept
• Measures detecting faults in memory
and logic
• Measures to detect single point and
latent faults
• Quantitative out of context analysis of
functional safety (FMEDA) tailored to
application specifics
• Safety manual and FMEDA report
available
• Boot flash authentication and fault
detection and correction using AES-128
and two-dimensional parity.
• Double and triple fault detection and
single fault correction scheme for
external DDR-RAM including address/
page fault detection.
• Fault encapsulation by hardware for
redundant executed application
software on multiple core cluster.
• Structural software based self test
routines providing high diagnostic
coverage.
• Same as S32V234
Debug • Standard JTAG
• 16-bit Trace port, Serial Wire Output
port
• Same as S32V234
Timers • General purpose timers (FTM) • Same as S32V234
Table continues on the next page...
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S32V234 Data Sheet, Rev. 8, 01/2019
6 NXP Semiconductors