Datasheet

1. See Table 4-9 2.5 and 5.0 GT/s Transmitter Specifications in PCI Express Base Specification for further details.
Table 49. PCI Express receiver specifications
1
Symbol Parameter 2.5 GT/s 5.0 GT/s Units
UI Unit Interval
399.88 (min)
400.12 (max)
199.94 (min)
200.06 (max)
ps
V
RX-DIFF-PP-CC
Differential Rx peak-
peak voltage for
common Refclk Rx
architecture
0.175 (min)
1.2 (max)
0.120 (min)
1.2 (max)
V
T
RX-EYE
Receiver eye time
opening
0.40 (min) N/A UI
T
RX-TJ-CC
Max Rx inherent timing
error
N/A 0.40 (max) UI
T
RX-DJ-DD-CC
Max Rx inherent
deterministic timing
error
N/A 0.30 (max) UI
1. See Table 4-12 2.5 and 5.0 GT/s Receiver Specifications in PCI Express Base Specification for further details.
6.5.7 IIC timing
Table 50. IIC SCL and SDA input timing specifications
Number Symbol Parameter Value Unit
Min Max
1 — D Start condition
hold time
2 — IP bus cycle
1
2 — D Clock low time 8 — IP bus cycle
1
4 — D Data hold time 25 — ns
6 — D Clock high time 4 — IP bus cycle
1
7 — D Data setup time 250 (standard
mode); 100 (fast
mode)
2
— ns
8 — D Start condition
setup time (for
repeated start
condition only)
2 — IP bus cycle
1
9 — D Stop condition
setup time
2 — IP bus cycle
1
1. Inter Peripheral Clock is the clock at which the IIC peripheral is working in the device
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 59