Datasheet

Table 47. MDIO interface timing specification (continued)
ID Parameter Symbols Min Max Unit
MDIO Output Timing
MDC1 MDC to MDIO Valid t
DVO
— 50 ns
MDC2 MDC to MDIO Invalid t
HO
10 — ns
MDIO Input Timing
MDC3 MDIO Input Setup time t
SUI
50 — ns
MDC4 MDIO Input Hold time t
HI
0 — ns
6.5.6 PCI Express specifications
The PCI Express link conforms to the PCI Express Base Specification, Revision 2.1. The
following summary of Transmitter and Receiver specifications are copied directly from
the Base Specification. Consult the Base Specification for additional details.
Table 48. PCI Express transmitter specifications
1
Symbol Parameter 2.5 GT/s 5.0 GT/s Units
UI Unit Interval
399.88 (min)
400.12 (max)
199.94 (min) 200.06
(max)
ps
V
TX-DIFF-PP
Differential p-p Tx
voltage swing
0.8 (min)
1.2 (max)
0.8 (min)
1.2 (max)
V
V
TX-DE-RATIO-3.5dB
Tx de-emphasis level
ratio
3.0 (min)
4.0 (max)
3.0 (min)
4.0 (max)
dB
V
TX-DE-RATIO-6dB
Tx de-emphasis level
N/A 5.5 (min)
6.5 (max)
dB
T
MIN-PULSE
Instantaneous lone
pulse width
Not specified 0.9 (min) UI
T
TX-EYE
Transmitter Eye
including all jitter
sources
0.75 (min) 0.75 (min) UI
T
TX-EYE-MEDIAN-to-MAX-
JITTER
Maximum time between
the jitter median and
max deviation from the
median
0.125 (max) Not specified UI
T
TX-HF-DJ-DD
Tx deterministic jitter >
1.5 MHz
Not specified 0.15 (max) UI
T
TX-LF-RMS
Tx RMS jitter < 1.5 MHz Not specified 3.0 ps RMS
BW
TX-PLL
Maximum Tx PLL
bandwidth
22 (max) 16 (max) MHz
BW
TX-PLL-LO-3dB
Minimum Tx PLL BW
for 3 dB peaking
1.5 (min) 8 (min) MHz
BW
TX-PLL-LO-1dB
Minimum Tx PLL BW
for 1 dB peaking
Not specified 5 (min) MHz
PKG
TX-PLL2
Tx PLL peaking with 5
MHz min BW
Not specified 1.0 (max) dB
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
58 NXP Semiconductors