Datasheet

6.5.5.4 Receive and Transmit signal timing specifications for RGMII
interfaces
This section provides timing specs that meet the requirements for RGMII interfaces for a
range of transceiver devices.
Table 46. Receive signal timing for RGMII interfaces
Characteristic Symbol RGMII Mode Unit
Min Typ Max
Clock cycle duration T
cyc
, 1
7.2 — 8.8 ns
Data to clock output skew at transmitter T
skewT
, 2
-500 — 500 ps
Data to clock input skew at receiver T
skewR
3
1 — 2.6 ns
Duty cycle for Gigabit Duty_G
3
45 — 55 %
Duty cycle for 10/100T Duty_T
3
40 — 60 %
Rise/fall time (20–80%) Tr/Tf - — 0.75 ns
1. For 10 Mbps and 100 Mbps, T
cyc
will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
2. For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an
additional delay of greater than 1.5 ns and less than 2 ns will be added to the associated clock signal. For 10/100, the max
value is unspecified.
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as
long as minimum duty cycle is not violated and stretching occurs for no more than three T
cyc
of the lowest speed
transitioned between.
TskewT
TXEN
TXERR
RGMII_TXC (at transmitter)
RGMII_TXDn (n = 0 to 3)
RGMII_TX_CTL
Figure 39. RGMII Transmit signal timing diagram original
TskewR
RXDV
RXERR
RGMII_RXDn (n = 0 to 3)
RGMII_RX_CTL
RGMII_RXC (at receiver)
Figure 40. RGMII Receive signal timing diagram original
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
56 NXP Semiconductors