Datasheet

t
CYC
t
H
t
S
t
PWH
RX_CLK
(Input)
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 37. MII receive signal timing diagram
Table 44. Receive signal timing for MII interfaces
Characteristic Symbol MII Mode Unit
Min Typ Max
RX_CLK clock period (100/10 MBPS) t
CYC
- 40/400 - ns
RX_CLK duty cycle, t
PWH
/t
CYC
- 35 50 65 %
Input setup time before RX_CLK t
S
5 - - ns
Input hold time after RX_CLK t
H
5 - - ns
t
CYC
t
D
t
PWH
TX_CLK
(Input)
TXDn,
TX_EN,
TX_ER
(Output)
Note: Device pins applicable to MII interface are applicable to TMII interface,
and operates at 50 MHz reference clock.
t
HO
Figure 38. MII transmit signal timing diagram
Table 45. Transmit signal timing for MII interfaces
Characteristic Symbol MII Mode Unit
Min Typ Max
TX_CLK clock period (100/10 MBPS) t
CYC
- 40/400 - ns
TX_CLK duty cycle, t
PWH
/t
CYC
- 35 50 65 %
TX_CLK to Output Valid t
D
- - 25 ns
TX_CLK to Output Invalid t
HO
2 - - ns
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 55