Datasheet

Ethernet Controller (ENET) Parameters
6.5.5.1 Ethernet Switching Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. For MII and
RMII mode, output load is equal to 25 pF and pad settings are SIUL2_MSCRn[DSE] =
101 and SIUL2_MSCRn[SRE] = 11. For RGMII, output load is 5 pF and pad settings are
SIUL2_MSCRn[DSE] = 111 and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
6.5.5.2 Receive and Transmit signal timing specifications for RMII
interfaces
This section provides timing specifications that meet the requirements for RMII
interfaces for a range of transceiver devices.
Table 43. Receive signal timing for RMII interfaces
Symbol Characteristic RMII Mode Unit
Min Max
— EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz
E3, E7 RMII_CLK pulse width high 35% 65% RMII_CLK period
E4, E8 RMII_CLK pulse width low 35% 65% RMII_CLK period
E1 RXD[1:0], CVS_DV, RXER to RMII_CLK setup 4 — ns
E2 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns
E6 RMII_CLK to TXD[1:0], TXEN valid — 14 ns
E5 RMII_CLK to TXD[1:0], TXEN invalid 2 — ns
6.5.5
Ethernet Controller (ENET) Parameters
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 53