Datasheet

Table 41. TxD output characteristics (continued)
Name Description
1
Min Max Unit
dCCTxD
01
Sum of delay between Clk to Q of
the last FF and the final output
buffer, rising edge
- 25 ns
dCCTxD
10
Sum of delay between Clk to Q of
the last FF and the final output
buffer, falling edge
- 25 ns
1. TxD pin load maximum 25 pF.
dCCTxD
10
dCCTxD
01
TxD
PE_Clk
*
*
FlexRay Protocol Engine Clock
Figure 34. TxD signal propagation delays
6.5.4.4
RxD
Table 42. RxD input characteristics
Name Description Min Max Unit
C_CCRxD Input capacitance on RxD pin - 7 pF
uCCLogic_1 Threshold for detecting logic high 35 70 %
uCCLogic_0 Threshold for detecting logic low 30 65 %
dCCRxD
01
Sum of delay from actual input to the D input of
the first FF, rising edge
- 10 ns
dCCRxD
10
Sum of delay from actual input to the D input of
the first FF, falling edge
- 10 ns
FlexRay
S32V234 Data Sheet, Rev. 8, 01/2019
52 NXP Semiconductors